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Instead of panic immediately when these instructions are executed, an
UndefinedInstruction fault is returned. In FS mode (not currently
implemented), this is the fault that should, to my knowledge, be triggered in
these situations and should be handled using the normal architected
mechanisms. In SE mode, the fault causes a panic when it's invoked that gives
the same information as the instruction did. When/if support for speculative
execution of ARM is supported, this will allow a mispeculated and unrecognized
and/or unimplemented instruction from causing a panic. Only once the
instruction is going to be committed will the fault be invoked, triggering the
panic.
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Shifting to the right of a signed value when the MSB is one is technically
undefined behavior, even though in my experience it's done the "right thing"
and sign extended the value. This replaces the arithmetic right shift code in
ARM that uses that coincidence with some code that relies on bit math.
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The shift amount when taken from a register is supposed to be truncated to an
8 bit value.
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This code doesn't use the parser at all, and moving it out reduces the
conceptual complexity of that code.
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The macroop should never be executed, only it's microops will.
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Fix so it works for older gccs.
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--HG--
rename : src/arch/arm/isa/formats/basic.isa => src/arch/arm/isa/templates/basic.isa
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Delete the now empty formats/util.isa.
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instructions.
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processing ones.
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