summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2019-10-30sparc: Create a helper functions to install firmware images.Gabe Black
The first function handles the repetitive process of creating an ObjectFile for a particular purpose and checking if that was successful. The second conditionally offsets the images in case they were, for instance, loaded from an ELF file which already had them in the right place. It offsets them so that their entry point (which will be zero for raw images) lines up with the appropriate entry address (which will be at the start of raw images). This is more correct in more cases, and also removes a lot of redundancy. There's still a lot of redundancy in the code which sets up the symbol tables, but there are some irregularities which make that harder to wrap in a helper function. Change-Id: I2fee8b2175faff284ff9e007307f7769043497a1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21469 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add a repeated value pattern to compressorsDaniel R. Carvalho
The repeated value pattern checks if values are composed of multiple instances of the same value. If successful, the bits of the repeated value are included only once in the compressed data. Change-Id: Ia7045b4e33a91fd8d712fe1ca689f7f8cb4e5feb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21153 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Inform unused bits instead of bytes in compressor patternDaniel R. Carvalho
Increase pattern precision by giving the number of unmatched bits instead of bytes. Change-Id: I5efbe9c31672cc973b4c89c741cdc8cc28d26285 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21152 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add a masked const value pattern to compressorsDaniel R. Carvalho
The masked pattern compares values to masked const non-dictionary values to determine whether these match. If successful, the bits that do not match must be added to the compressed data. Change-Id: I4c53568694dab916136fe384cb2ee10e554f7136 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21151 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add a masked pattern to compressorsDaniel R. Carvalho
The masked pattern compares masked values to masked dictionary entries to determine whether these values match. If successful, the bits that do not match must be added to the compressed data. Change-Id: I4b1c8feb0faa99576382b54a73a20c353f965d2a Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21150 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add an uncompressed pattern to compressorsDaniel R. Carvalho
The uncompressed pattern always stores the original data, and therefore it is always successful. All of the derived classes of the dictionary compressor must have this pattern as the last pattern of the pattern factory. Change-Id: I2a38fd56630d88ef8b918220dc4c2824a196a8a2 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21149 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Templatize DictionaryCompressorDaniel R. Carvalho
Templatize DictionaryCompressor so that the dictionary entries' sizes can be changed. Change-Id: I3d89e3c692a721cefcd7e3c55d2ccdefa425f614 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21148 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-10-29mem-cache: Factor out CPack's dictionary functionalityDaniel R. Carvalho
Factor out dictionary functionality of CPack, so that it can be used easily for other compressors. As a side effect, create an addToDictionary function to allow subclasses to chose how to handle insertion. Change-Id: I02fae4e98b02db5a40467ec470b71020d5e867cb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21147 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-10-29mem-cache: Use shouldAllocate() instead of CPack's decompress()Daniel R. Carvalho
Split decompression functionality using the proper function to determine if a dictionary entry should be allocated after decompression or not. Change-Id: I4995304f4c4508c03c9fc1685f04511622969556 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21146 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-10-29mem-cache: Limit compression sizeDaniel R. Carvalho
Add a threshold so that if the compressed size is greater than it, the compression is abandoned, and the data is considered uncompressible. Change-Id: Ic416195b06ec440a40263b75bd0f0383cde2ea6a Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21144 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-10-29mem-cache: Do not try to compress dataless packetsDaniel R. Carvalho
Fix filling blocks so that packets that do not contain data do not generate a compression attempt. This can happen, for example, with invalidation responses, which will trigger a packet data access assertion. Change-Id: I2a1e7983657f6e5e770b148ab62c9de9ac3986ac Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22164 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem: Fix DRAM controller to operate on its own address spaceNikos Nikoleris
Typically, a memory controller is assigned an address range of the form [start, end). This address range might be interleaved and therefore only a non-continuous subset of the addresses in the address range is handed by this controller. Prior to this patch, the DRAM controller was unaware of the interleaving and as a result the address range could affect the mapping of addresses to DRAM ranks, rows and columns. This patch changes the DRAM controller, to transform the input address to a continuous range of the form [0, size). As a result the DRAM controller always operates on a dense and continuous address range regardlesss of the system configuration. Change-Id: I7d273a630928421d1854658c9bb0ab34e9360851 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19328 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Avoid promotion of incompatible deferred targetsNikos Nikoleris
Often a request that hits on an MSHR has to be deferred as it can't be serviced by the current response. For example, a request that requires writable has to be deferred when the response is expected to bring in a read-only copy of the block. However, there are cases where the response, although not expected to do so, brings a writable copy and as a result we also service deferred targets. In such cases, we promote deferred targets up until the first that can't be serviced by the current response (e.g., cache maintainance operation). If the first deferred target is incompatible we don't promote any targets at all. Change-Id: Ib3e13be51120b7c0f0053b83b76bde03e1b7dd4e Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22127 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-29mem-cache: Fix MSHR whole line write trackingNikos Nikoleris
The MSHR keeps track of outstanding writes and services them as a whole line write whenever possible. To do this the outstanding writes have to be compatible (e.g., not strictly ordered). Prior to this change, due to this tracking mechanism, the MSHR would not service a WriteLineReq with flags that do not allow merging as a full line write even if it was the first target triggering an assertion. This changeset fixes this bug. Change-Id: I2cbf5ece0c108c1fcfe6855e8f194408d5ab8ce2 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22126 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-28tests, base: Fixed incorrect implementation of StrTest.ToLower test.Bobby R. Bruce
Change-Id: I96672052f8c9da9d4f61ff0e8eed324032b1afac Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22123 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25mips,riscv: Get rid of some Alpha cruft in these System classes.Gabe Black
The consolePanicEvent pointer and addConsoleFuncEvent template were inherited from Alpha and were not used (and probably make no sense) for MIPS or RISCV which (to my knowledge) don't have the idea of a "console" binary. Change-Id: I109b866a65f69c7334062f7304c7b18acc51d99d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21782 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-25cpu: Get rid of the nextInstEventCount method.Gabe Black
This was only used by the KVM CPU, and it has access to all it needs to figure out that value locally without requiring all the ThreadContexts to implement an equivalent function. Change-Id: I17a14ce669db2519edf129db761ebd8dc3bd4129 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22114 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Get rid of the serviceInstCountEvents method.Gabe Black
This was useful when transitioning away from the CPU based comInstEventQueue, but now that objects backing the ThreadContexts have access to the underlying comInstEventQueue and can manipulate it directly, they don't need to do so through a generic interface. Getting rid of this function narrows and simplifies the interface. Change-Id: I202d466d266551675ef6792d38c658d8a8f1cb8b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22113 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25fastmodel: Use getCurrentInstCount for totalInsts().Gabe Black
This had been using a custom totalInsts method on the iris ThreadContext, but since that's equivalent to what the totalInsts method does only through a different mechanism, we can drop that and use getCurrentInstCount instead. Change-Id: I058fec13e81f28285281e136635d53a2e849cb47 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22112 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25fastmodel: Implement getCurrentInstCount.Gabe Black
This uses the step counter the iris API provides. Change-Id: Ic916888fa256d0aa65042d3e6695d9bf4ba32c86 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22111 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Switch off of the CPU's comInstEventQueue.Gabe Black
This switches to letting the ThreadContexts use a thread based/local comInstEventQueue instead of falling back to the CPU's array. Because the implementation is no longer shared and it's not given where the comInstEventQueue (or other implementation) should be accessed, the default implementation has been removed. Also, because nobody is using the CPU's array of event queues, those have been removed. Change-Id: I515e6e00a2174067a928c33ef832bc5c840bdf7f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22110 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Access inst events through ThreadContext instead of the CPU.Gabe Black
Also delete the CPU interface. Change-Id: I62a6b0a9a303d672f4083bdedf393f9f6d07331f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22109 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Delegate comInstEventQueue methods to the ThreadContexts.Gabe Black
These then just use the comInstEventQueue array from the CPU, but soon they will actually be self contained and allow the thread context to use whatever mechanism it wants. Also, now that the thread contexts need to exist before instruction count based events can be scheduled, setting up max instruction based events needs to happen in init after the CPU subclasses have had a chance to set up the threadContexts vector. Change-Id: I34bb401633d277a60be74e30d5a478a149b972ea Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22108 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Make accesses to comInstEventQueue indirect through methods.Gabe Black
This lets us move the event queue itself around, or change how those services are provided. Change-Id: Ie36665b353cf9788968f253cf281a854a6eff4f4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22107 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu,sim: Delegate PCEvent scheduling from Systems to ThreadContexts.Gabe Black
The System keeps track of what events are live so new ThreadContexts can have the same set of events as the other ThreadContexts. Change-Id: Id22bfa0af7592a43d97be1564ca067b08ac1de7c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22106 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Make the ThreadContext a PCEventScope.Gabe Black
Both the thread and system's PCEventQueue are checked when appropriate. Change-Id: I16c371339c91a37b5641860d974e546a30e23e13 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22105 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu,sim: Get rid of a bunch of conditional compilation for PCEvents.Gabe Black
These can now be built without referring to anything in ThreadContext and so can be built even with the NULL ISA. This means the pcEventQueue can be unconditionally built into the System class. Even though the pcEventQueue is going away, this still makes it possible for System to be a PCEventScope unconditionally. Change-Id: Ia342bb7972b1b5ce95033176d72af4bfa343560f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22104 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Don't print the CPU name when a (Break|Panic)PCEvent happens.Gabe Black
This requires reaching into the threadcontext to access the CPU pointer, and also isn't all that useful since it's more important what event happened, not what CPU happened to be running the code at that time. Change-Id: I368707c804dff9bd349f3261bdcd08be55c5d04a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22103 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Pass the address to check into the PCEventQueue service method.Gabe Black
This prevents having to access it from within the ThreadContext. Change-Id: I34f5815a11201b8fc41871c18bdbbcd0f40305cf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22102 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25sim: Make the System object a PCEventScope.Gabe Black
This abstracts away the raw PCEventQueue managed by the System. Change-Id: I04d773e6be90a891884a76841f15c3eecd5796ed Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Stop checking for PC changes when servicing a PCEventQueue.Gabe Black
First of all, this would arbitrarily skip events based on when they were encountered in the queue. Second, this is one of the three places where the ThreadContext is actually accessed in pc_event.cc. By removing this and the other uses, this file can be included even when using the NULL ISA, and a lot of #ifdefs can be removed. Change-Id: If81f5e9ff9d3f9833145fec0b6062b4bda8d2e47 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22100 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Create a PCEventScope class to abstract the scope of PCEvents.Gabe Black
This abstraction will allow scheduling PCEvents for a particular ThreadContext, all contexts on a CPU, all contexts in a system, etc., and delegates scheduling and removing events to each particular scope. Right now the PCEventQueue is the only implementor of the PCEventSCope interface. Change-Id: I8fb62931511136229915c2e19d36aae7ffdec9df Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22099 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-24tests: Added GTests for base/str.ccBobby R. Bruce
Adding these tests supercedes the unittest/strnumtest.cc and unittest/tokentest.cc tests. They have thereby been removed. Function "to_number" in base/str.hh previously failed to cast negative float/double numbers. This was due to the use of std::numeric_limits<T>::min() instead of std::numeric_limits<T>::lowest() to determine whether a string-to-float/double conversion was "Out of range". Tests "StrTest.ToNumberFloatNegative" and "StrTest.ToNumberDoubleNegative" exposed this bug. It has been fixed. Methods "split_first" and "split_last" in base/str.hh have had their documentation updated to remove abiguity in their functionality. Change-Id: I16e0fe40d884e22dd010db4045857eb6e7f33d4a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22084 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-24cpu, sim-se: don't wake up threads that are awake in futexCiro Santilli
FutexMap::wakeup is called when the futex(TGT_FUTEX_WAKE syscall is done. FutexMap maintains a list of sleeping threads for each futex address added on FutexMap::suspend, and entries are removed from the list at FutexMap::wakeup. The problem is that this system was not taking into account that threads can be woken up by memory accesses to locked addresses via the path: SimpleThread::activate BaseSimpleCPU::wakeup AbstractMemory::checkLockedAddrList AbstractMemory::access DRAMCtrl::recvAtomic CoherentXBar::recvAtomicBackdoor SimpleExecContext::writeMem which happens on trivial pthread examples on ARM at least. The instruction that locked memory in those test cases was LDAXR. This could lead futex(TGT_FUTEX_WAKE to awake a thread that is already awake but is first on the sleeping thread list, instead of a sleeping one, which can lead all threads to incorrectly sleep and in turn to "simulate() limit reached". To implement this, ThreadContext::activate return now returns a boolean that indicates if the state changed. suspend and halt are also modified to also return a boolean in the same case for symmetry, although this is not strictly necessary for the current patch. Change-Id: Ia6b4d3e6148c64721d810b8f1fffaa208a394b06 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21606 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-24sim-se: fix futexFunc TGT_FUTEX_WAIT always selects bitsetCiro Santilli
Change-Id: I3e2bd1dd34d7cc00b2685547ab74b56bd8126128 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21605 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-23fastmodel: Add string constructors which delegate to const char * ones.Gabe Black
Change-Id: I22d88111409fc477c135b15c8f898adad4f6d4ab Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21502 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-23cpu: Apply the ARM TLB rework to the O3 checker CPU.Gabe Black
The TLBs now create the stage 2 MMUs as children, and since those are specialized for instruction and data, the CPU needs to use ArmITB or ArmDTB instead of ArmTLB which is the base class without an MMU. This was changed for the BaseCPU and SimpleCPU checker already, but the TLBs are added in the O3 checker CPU as well. Change-Id: I498f247f376c8721fb70ce26c0f1b0815b12fe2d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22039 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-23arch: Drop sysctl support if built against glibcTommaso Marinelli
Since glibc 2.30 the sysctl() function has been declared deprecated and it will be deleted in future versions. This patch removes the support for the sysctl system call in SE mode (which is currently serviced calling the sysctl() function) if gem5 is built against glibc, keeping it with other libc implementations, as a temporary measure to prevent the generation of a compilation error. Note that this system call in gem5 is only supported for the arm/freebsd architecture. Change-Id: Ie5fcb983d15c0a27c7820d24250d7ae5dbe12355 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21519 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-22configs: Clean setupBootLoader signatureGiacomo Travaglini
This is because the bus parameter is not used anymore Change-Id: I27aa8cc064904a6e3e0376f61eb7db74ea1a4d6c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22002 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-22dev-arm, configs: Using _on_chip_memory for on chip memoryGiacomo Travaglini
This patch is pulling the on-chip memory outside of the on_chip_devices list. The external interface will be more or less the same: configuration scripts will still use the attachOnChipIO method; a new kw argument has been added in order to store mem_ports. We want to provide to on-chip memory the same mechanism used when collecting on-chip dma ports. This is needed when using Ruby, since we need to pass a non None mem_ports to prevent the bootmem to be wired to the bus. Change-Id: Ifc519c3072dc5de1530772c70c80dc2094e2c54c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22000 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-21cpu: Apply the ARM TLB rework to the checker CPU.Gabe Black
The TLBs now create the stage 2 MMUs as children, and since those are specialized for instruction and data, the CPU needs to use ArmITB or ArmDTB instead of ArmTLB which is the base class without an MMU. This was changed for the BaseCPU already, but the TLBs are added in the checker CPU as well. Change-Id: Ide8ce950622b40f69c37bbe2ea0d22295b76d7a6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21979 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-19cpu,arm: Push the stage 2 MMUs out of the CPU into the TLBs.Gabe Black
This regularizes the TLB setup in the CPU so that ARM is no longer a special case with extra objects. Change-Id: I739b82578ff74f8f9777cd7e34cd5227b47b186c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21842 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-19arch: Remove the "interrupts.hh" switching header file.Gabe Black
That switching header is no longer necessary since everything outside of the ISA can use the BaseInterrupts class. Change-Id: Ie3ed45c38fec24234ff51fb05ba94f6f3cd02afd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20832 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-19arch: Make a base class for Interrupts.Gabe Black
That abstracts the ISA further from the CPU, getting us a small step closer to being able to build in more than one ISA at a time. Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-18dev-arm: Check for gem5 extensions in GicV2Tiago Muck
Using GicV2 without setting the gem5_extensions parameter in a config with more than 8 is not allowed to prevent overflow of the 8-bit mask. Change-Id: I780c6985e8f44ed780b4f74f9a27805124e23a7b Signed-off-by: Tiago Mück <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19288 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-18tests: Added GTests for base/bitfield.hhBobby R. Bruce
In addition to the tests, a more detailed explanation of how "insertBits(..)" functions has been included in its doxygen documentation. The previous explanation was ambigious and led to confusion. Change-Id: I2ae8608733ebaa8f8f726cbb3a2cd8639b69c6b7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21700 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-18arch: Get rid of the unused GenericTLB.Gabe Black
Nothing is using it, and it's actually not use*able* at the moment because it doesn't have implementations for all the pure virtual methods that exist in the BaseTLB class. Change-Id: I03d47c2e116f354c7247a2fa19a9f33dfe4c5eec Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21841 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-18cpu: Turn the stage 2 ARM MMUs from params to children.Gabe Black
These aren't referred to in the C++, so there's no reason for them to be parameters. By making them children, they can still be modified, replaced wholesale, or even replaced by an entirely different object to, for instance, mask them when they're not needed. Change-Id: Ic7f144a3cd3d1fca12fec220918aa72af885f61c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21839 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-18x86: Turn the local APIC Interrupts class into a SimObject.Gabe Black
It will no longer be a PioDevice or a ClockedObject, but will carry forward the little bits and pieces of those classes that it was using. Those are a PIO port for memory mapped register accesses, and a clock domain parameter for setting the apic tick frequency. This brings the x86 Interrupts class in line with the Interrupts of the other ISAs so that they can inherit from a standard base class. Change-Id: I6b25fa21911b39a756e0cf9408c5489a81d6ca56 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20829 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-18tests: Added GTests for base/atomicio.ccBobby R. Bruce
Change-Id: I586a06c70f4e7331b4a31208ef7831e8473509c5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21699 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-20 18:15:04 +0000