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2018-02-07arch-arm: Change the type of fault for dc ivac instructionsNikos Nikoleris
Change-Id: I00f957a3bc4721a66db62b1257f10e9019a94608 Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7829 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-02-07arch-arm: Unify permission checks for dc * instructionsNikos Nikoleris
Change-Id: Ib47f4134e3f0a580e5356d384a5d3b293c1af7be Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7828 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Check cache maintenance insts for permission faultsNikos Nikoleris
In AArch32, data cache maintenance instructions that operate by VA do not generate permission faults. In AArch64, a data cache invalidate instruction can generate a permission fault when there are no write permissions to the specified VA. Data cache clean and data cache clean and invalidate instructions do not generate permission faults. Checks for external aborts are also bypassed for data cache maintenance instructions. Change-Id: Iea5bc665e4cf66d528e36b671535b66637c4b224 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7827 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Turn dc ivac to dc civac when some conditions are metNikos Nikoleris
The Arm ARM defines that at EL1 a data cache invalidate instruction performs a data cache clean and invalidate operation if all of the following apply: * EL2 is implemented, * HCR_EL2.VM is set to 1, * SCR_EL3.NS is set to 1 or EL3 is not implemented. This changeset implements this behavior. Change-Id: I6b6aef2f4b1e7eb107c069fdb0a10f4aa8e6b196 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7826 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Fix printing of the data cache maintenance instructionsNikos Nikoleris
Change-Id: I2322c7bf65b38cb07a1ea2b5dc25dfc5a0496cf0 Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7825 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-02-07arch-arm: Fix cache line size for cache maintenace instNikos Nikoleris
Cache maintenance operations operate on whole cache blocks. This changeset uses the system cache line size as the size of the cache maintenance requests and masks the lower bits of the effective address. Change-Id: I6e7aefff51670c8cac39e4e73db21a0c5a0b7aef Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7824 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Fault when dc ivac is executed from EL0Nikos Nikoleris
A previous change enabled execution of dc ivac from EL0 when SCTLR_EL1.UCI=1. The Arm ARM specifies that dc ivac is the only data cache maintenance operation by VA that cannot be executed from EL0. This changeset essential reverts the change: 8d43922 arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1 Change-Id: Ia25fab13846a151f548e649a16067feb1ff65c9c Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7823 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07mem-cache: Only pendingModified MSHRs can satisfy CMO snoopsNikos Nikoleris
We set the satisfied flag when a cache clean request encounters: 1) a block with the dirty bit set, or 2) a pending modified MSHR which means that the cache will get copy of the block that will be soon modified. This changeset fixes a previous bug that set the satisfied flag on snooping MSHR hits even the pendingModified flags was not set. Change-Id: I4968c4820997be5cc1238148eea12a1ba39837d4 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7822 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-02-07mem-cache: Cleaned blocks should be marked as not writableNikos Nikoleris
A writeclean packet writes a dirty block to the memory below and therefore sets the dirty flag for the block when the memory below is a cache. If the block was also marked as writable it can satisfy future write requests without further requests/snoops. This can lead to multiple copies of the same block marked as dirty which is not allowed. This changeset clears the writable flag from the cleaned block to prevent the cache from satisfying future write requests without sending a downstream request. Change-Id: I14d3c62fd33f81b1a8ba62374c8565ccab00a6fe Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7821 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-02-07arch-arm: Change function name for banked miscregsGiacomo Travaglini
This commit changes the function's name used for retrieving the index of a security banked register given the flatten index. This will avoid confusion with flattenRegId, which has a different purpose. Change-Id: I470ffb55916cb7fc9f78e071a7f2e609c1829f1a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7982 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Fix AArch32 SETEND InstructionGiacomo Travaglini
This patch fixes AArch32 SETEND instruction, which was previously executed unconditionally without checking (H)SCTLR.SED field. This bit enables/disables the trapping of the instruction. Change-Id: Ib3d2194c8d16c34ec2a9ab3e8090081900c1e42e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7981 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Correct Illegal Exception Return detectionGiacomo Travaglini
Fixed Illegal Exception Return detection, which was not covering all the documented cases. Change-Id: If08ddc1490d1c0a1fccee1489d116384770ce0a5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7223 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: ELUsingAArch32K from armarm pseudocodeGiacomo Travaglini
This patch implements the ELUsingAArch32K pseudocode, which is returning true if the provided Exception Level is using A32 ISA, but it is not panicking (quitting simulation) if the information is unknown (see documentation). The panicking is the current behaviour of the ELIs32 utility in gem5. Change-Id: Iad7b56077d7e0f8ee223b5b9593cb8097f26bb29 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7222 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: isSecureBelow from armarm pseudocodeGiacomo Travaglini
This patch introduces the inSecureBelow pseudocode function defined in the armarm documentation. It also replaces the inSecureState function call which was improperly used in ELIs32: we might be in secure state (EL3), but with non-secure lower ELs (SCR.NS = 1). Change-Id: I01febcb54392ad4e51e785b4d5153aeb3437c778 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Chuan Zhu <chuan.zhu@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7221 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Fix incorrect assumptions in ELIs64Chuan Zhu
The state of EL1 wasn't determined correctly when running in secure mode if virtualisation was enabled. This changset updates the implementation to match the canonical behavior from the ARM ARM. Change-Id: I7ed6f5c003617773603f678667aac069d73b6f62 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7141 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-02-06mem-cache: Remove extra numSets zero check.Daniel R. Carvalho
numSets is unsigned, so it cannot be lower than 0. Besides, isPowerOf2(0) is false by definition (and implemmentation*), so there is no need for the double check. * As presented in base/intmath.hh Change-Id: I3f6296694a937434feddc7ed21f11c2a6fdfc5a9 Reviewed-on: https://gem5-review.googlesource.com/7901 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-06mem: Standardize mem folder header guardsDaniel R. Carvalho
Standardize all header guards in the mem directory according to the most frequent patterns. In general they have the form: mem: __FOLDER_TREE_FILE_NAME_HH__ ruby: __FOLDER_TREE_FILENAME_HH__ Change-Id: I983853e292deb302becf151bf0e970057dc24774 Reviewed-on: https://gem5-review.googlesource.com/7881 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-02-05base: Update #includes for bitunion.hh.Gabe Black
<iostream> isn't actually used anywhere in bitunion.hh. The templated hash struct type is defined in <functional> and should be included explicitly. Change-Id: I8691ccb2f9e28a01610ae8bb4d9591b07cb7320b Reviewed-on: https://gem5-review.googlesource.com/7781 Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de> Maintainer: Gabe Black <gabeblack@google.com>
2018-02-05cpu: MinorCPU handling IsSquashAfter flagGiacomo Travaglini
MinorCPU was not handling IsSquashAfter flagged instructions. The behaviour was to force a branch (hence enforcing refetching) for SerializeAfter instructions only. This has now been extended to SquashAfter in order to correctly support ISB barrier instruction behaviour. Change-Id: Ie525b23350b0de121372d3b98b433e36b097d5c4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5702 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-05arch-arm: Removing Serializing flag from ISBGiacomo Travaglini
ISB Serializing behaviour is guaranteed by IsSquashAfter, which is inherently serializing; when instruction is commited, consecutive instructions are flushed and refetched. Change-Id: I05e61b4cf9f01113d95b1502c996d04cbd69b759 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5701 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-02base: Fix unused function warningNikos Nikoleris
After refactoring the remote gdb interface, break_type is declared as const function and is only used as a parameter to DPRINTF function calls. This means that it is seen as unused when compiling gem5.fast. This changeset fixes the warning. Change-Id: Iea89b66c53c62341c043d8bd3838ebc27ee333bc Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7741 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-02-01alpha: fix for no 'break' in the case statementSujay Phadke
gem5 won't compile correctly since g++ will throw a warning (error) that the next case statement below this one is reachable since there is no 'break' statement. Signed-off-by: Sujay Phadke Change-Id: Icab646ee5abcfeb6ba3e690909042927b4003eba Reviewed-on: https://gem5-review.googlesource.com/7521 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-31arch-x86: consistent style of comments in system filesChristian Menard
Change-Id: I9f208819b8c1a5c46a77262eb533bb47adb2b905 Reviewed-on: https://gem5-review.googlesource.com/7701 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-30arch-x86: Granularity bit and segment limitMaximilian Stein
If set, the granularity bit indicates that the segment limit of segment descriptors shall be interpreted as number of 4K blocks rather than bytes. The high part (bit 48 to 51) of segment descriptor limits is only 4 bits wide while the low part (bit 0 to 15) spans 16 bits. Change-Id: Ie386224ca815275fdb31498fe68310ed9c62cc87 Reviewed-on: https://gem5-review.googlesource.com/7601 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-29riscv: Add overrides to various StaticInst methods.Gabe Black
This makes riscv compile with the version of clang(++) I have on my workstation. Change-Id: I0478616810fbc8a715fd61323b7e0f73676c8328 Reviewed-on: https://gem5-review.googlesource.com/7643 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-29base: Remove the ability to cprintf stringstreams directly.Gabe Black
The cprintf functions don't know ahead of time what format characters are going to be used with what underlying data types, and so any type must be minimally usable with the default specialization of format_integer, format_char, format_float and format_string. All of those functions ultimately print their parameter with out << data except the one which prints stringstreams. That function accesses the buffer of the string stream with .str(), and then prints that instead. That should technically work out ok as long as stringstreams are only printed using %s, but there's no way to guarantee that ahead of time. To avoid that problem, and because gem5 doesn't ever actually use the ability to print stringstreams directly, this change removes that feature and modifies the corresponding part of the unit test. If we ever do want to print the contents of a string stream, it won't be difficult to add a .str() to it. Change-Id: Id902eaff042b96b374efe0183e5e3be9626e8c88 Reviewed-on: https://gem5-review.googlesource.com/7642 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-29base: Delete commented out versions of the format_integer function.Gabe Black
If they're needed, they'd be fairly easy to recreate and are also available in the revision history. Change-Id: I5cf5e4b1271ce488016464048de69bc643dee4d9 Reviewed-on: https://gem5-review.googlesource.com/7641 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-29arch-arm: understandably initialize register permissionsCurtis Dunham
Move massive initialization routine to the bottom of miscregs.cc. Additionally, share register metadata across ISA instances by making lookUpMiscReg a static member of the ISA and only initializing it once. Change-Id: I6d6ab26200c4e781151cc6efd97ce2420e2bf4cc Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6803 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29arm: extend MiscReg metadata structuresCurtis Dunham
Implement proper handling of RES0/RES1 and RAZ/RAO bitfields. Change-Id: I344c32c3fb1d142acfb0521ba3590ddd2b1f5360 Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6802 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29arch-arm: understandably initialize register mappingsCurtis Dunham
The mappings for sharing a backing store between AArch32 and AArch64 system registers are made clearer using an initializer object. Change-Id: I29dcfab2797b4d36b3182342997edffde334a291 Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6801 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29arm: DT autogeneration - generate PCI nodeGlenn Bergmans
Enables automatic generation of Device Trees for RealView PCI host controllers. Note that some parts are more hard coded than you'd want, but this is due to the limited understanding the PCI host has of its configuration (i.e. it doesn't know all memory ranges). Fixing this, for now at least, went beyond the scope and intentions of the Device Tree generating code: use with care! Change-Id: I2041871e0eb4d04fb5191257c47dd38649d1c0cc Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5967 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29arm: DT autogeneration - Generate energy controller nodeGlenn Bergmans
Adds Device Tree methods for the energy controller to allow for DVFS simulations with automatically generated DTB files Change-Id: Id8682f07dff1bbe63987e757faa0694e03ee86ab Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5966 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29arm: DT autogeneration - autogenerate RealView Platform devicesGlenn Bergmans
Implements the Device Tree generating code for devices required by the RealView VExpress_GEM5_V1 platform Change-Id: I14244b2f3c028cbddba3c23ce7433fe3b301a0e8 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5965 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29arm: DT autogeneration - Generate memory nodeGlenn Bergmans
Implements a high level method for generating a Device Tree node for an AbstractMemory object. Change-Id: I544ec642f182f103df26de535fdfaf03b3787a08 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5964 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29arm: DT autogeneration - Generate cpus nodeGlenn Bergmans
Equips cpu models with a method to generate the cpu node. Note: even though official documentation requires that CPU ids start counting from 0 in every cluster, GEM5 requires a globally unique cpu_id. Change-Id: Ida3e17af3124a68ef7dbf2449cd034dfc3ec39df Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5963 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29arm: DT autogeneration - Device Tree generation methodsGlenn Bergmans
This patch adds an extra layer to the pyfdt library such that usage gets easier and device tree nodes can be specified in less code, without limiting original usage. Note to not import both the pyfdt and fdthelper in the same namespace (but generally fdthelper is all you need, because it supplies the same classes even when they are not extended in any way) Also, this patch lays out the primary functionality for generating a device tree, where every SimObject gets an empty generateDeviceTree method and ArmSystems loop over their children in an effort to merge all the nodes. Devices are implemented in other patches. Change-Id: I4d0a0666827287fe42e18447f19acab4dc80cc49 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5962 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29ext: DT autogeneration - Add PyFtd to m5 spaceGlenn Bergmans
This patch adds pyfdt.py to the m5.ext module. This is used in succeeding patches for generating and editing dtb files and flat device trees for DT autogeneration. The file is in the m5_root/src/python/m5/ext directory, as opposed to the m5_root/ext, because this library is part of the m5 object space and linking to the m5_root/ext directory from the SConscript file in src/python can not be done reliably. Linking from the root level SConscript is also not an option, because it doesn't have the PySource method defined. Cloned from: https://github.com/superna9999/pyfdt Commit: accbcd254584c9295a18878d32999d0c7c156f8e Version: 0.3 Change-Id: I928bdc912a9507d1f8a3290acf445c7cae496552 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5961 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29arm: make Arm GenericTimer a ClockedObjectCurtis Dunham
Within a device tree, the GenericTimer device needs to point (via phandle) to a clock domain which is itself also an object in the device tree. Within gem5, clock domains are managed by making all clocked SimObjects inherit from ClockedObject rather than SimObject. Without this change, the GenericTimer is unable to generate the appropriate clock domain phandle, and will crash during DTB autogeneration. Change-Id: I6d3fb6362847c6a01720b2f14b3d595d1e59f01f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4960 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-27base: Add an "override" to name() in the HardBreakpoint class.Gabe Black
clang reports an error otherwise and fails to compile. Change-Id: I3603d6c710641f1289e35c67f89a49f5cb71e95e Reviewed-on: https://gem5-review.googlesource.com/7582 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-27base: Get bitunions to compile on clang 3.8.Gabe Black
clang was getting very upset and interpretting a member function pointer as a call to the actual underlying function, and then complaining that it was a non-static function call without an instance. It seems what it was really upset about was that the class who's scope the member function pointer belonged to (the current class) wasn't done being defined. This *should* be ok as far as I can tell, but clang was having none of it. This change reworks how the type of the setter function arguments are determined to work around that limitation. The bitunion test was run with clang++ and g++ and both pass, and I've built gem5.opt for ARM successfully. Change-Id: Ib9351784a897af4867fe08045577e0247334ea11 Reviewed-on: https://gem5-review.googlesource.com/7581 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-23arch-x86: Adding clflush, clflushopt, clwb instructionsSwapnil Haria
This patch adds support for cache flushing instructions in x86. It piggybacks on support for similar instructions in arm ISA added by Nikos Nikoleris. I have tested each instruction using microbenchmarks. Change-Id: I72b6b8dc30c236a21eff7958fa231f0663532d7d Reviewed-on: https://gem5-review.googlesource.com/7401 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-23arch: Remove the "arch/tlb.hh" switching header.Gabe Black
This header is no longer used. Change-Id: I8da7f8618d647dd11c581818c13855c4e20d32d2 Reviewed-on: https://gem5-review.googlesource.com/7351 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-23tarch, mem: Abstract the data stored in the SE page tables.Gabe Black
Rather than store the actual TLB entry that corresponds to a mapping, we can just store some abstracted information (address, a few flags) and then let the caller turn that into the appropriate entry. There could potentially be some small amount of overhead from creating entries vs. storing them and just installing them, but it's likely pretty minimal since that only happens on a TLB miss (ideally rare), and, if it is problematic, there could be some preallocated TLB entries which are just minimally filled in as necessary. This has the nice effect of finally making the page tables ISA agnostic. Change-Id: I11e630f60682f0a0029b0683eb8ff0135fbd4317 Reviewed-on: https://gem5-review.googlesource.com/7350 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-23x86, mem: Rewrite the multilevel page table class.Gabe Black
The new version extracts all the x86 specific aspects of the class, and builds the interface around a variable collection of template arguments which are classes that represent the different levels of the page table. The multilevel page table class is now much more ISA independent. Change-Id: Id42e168a78d0e70f80ab2438480cb6e00a3aa636 Reviewed-on: https://gem5-review.googlesource.com/7347 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-20x86, mem: Don't try to force physical addresses on the system.Gabe Black
Use the system object to allocate physical memory instead of manually placing certain structures and then forcing the system to start other allocations after them in physical memory. Change-Id: Ie18c81645c3b648c64a6d7a649a0e50f7028f344 Reviewed-on: https://gem5-review.googlesource.com/7346 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2018-01-20x86, mem: Get rid of PageTableOps::getBasePtr.Gabe Black
Pass this constant into the page table constructor. Change-Id: Icbf730f18d9dfcfebd10a196f7f799514728b0fb Reviewed-on: https://gem5-review.googlesource.com/7345 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2018-01-20x86, mem: Pass the multi level page table layout in as a parameter.Gabe Black
Don't get it from a global constant declared in an ISA header file. Change-Id: Ie19440abdd76500a5e12e6791e6f755ad9e95af3 Reviewed-on: https://gem5-review.googlesource.com/7344 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-01-20arch, mem: Make the page table lookup function return a pointer.Gabe Black
This avoids having a copy in the lookup function itself, and the declaration of a lot of temporary TLB entry pointers in callers. The gpu TLB seems to have had the most dependence on the original signature of the lookup function, partially because it was relying on a somewhat unsafe copy to a TLB entry using a base class pointer type. Change-Id: I8b1cf494468163deee000002d243541657faf57f Reviewed-on: https://gem5-review.googlesource.com/7343 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-20base: Hide the BitUnion::__StorageType type.Gabe Black
Since this type is now accessible through a clean interface, hide it from anybody that tries to peak around the curtain. Change-Id: I1257b6675a45b8648be459ad8e8d0f27a6feee6b Reviewed-on: https://gem5-review.googlesource.com/7205 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-20arm, base: Generalize and move the BitUnion hash struct.Gabe Black
The ARM types.hh file defined an STL style hash structure to operate on the ExtMachInst, but it referred to the underlying storage type using internal typedefs in the BitUnion types. To avoid having to do that, this change adds a hash structure to bitunion.hh which will work on any BitUnion, and gets rid of the ARM ExtMachInst version. Change-Id: I7c1c84d61b59061fec98abaaeab6becd06537dee Reviewed-on: https://gem5-review.googlesource.com/7204 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
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