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2019-02-20config: Make parameter conversion handle integers in other bases.Gabe Black
Python's float() function/type can't handle hexadecimal notation, but int() can. Since there are also cases where converting to a float and then back to an int (or long) can cause rounding error, this change splits toFloat and toInteger apart and makes them call a worker function which accepts a conversion function which does the work of converting a numeric string into an actual number. in the case of toFloat, it still uses the standard float(), and in the case of toInteger it uses a lambda which wraps int(x, 0). Change-Id: Ic46cf4ae86b7eba6f55d731d1b25e3f84b8bb64c Reviewed-on: https://gem5-review.googlesource.com/c/16504 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-20x86: Call the base class's regStats in X86ISA::TLBBagus Hanindhito
When I try to build x86 architecture and run the se.py sample script with helloworld example, there is a panic warning stated "Not all stats have been initialized. You may need to add <ParentClass>::regStats() to a new SimObject's regStats() function." I see that in x86 tlb.cc, there is no initialization in regStats() function that causes memory allocation error in some machine which make gem5 exit abnormally. I add the BaseTLB::regStats(); on TLB::regStats() method and can solve the problem Change-Id: I8b62bebc15f896c3136ff4f8253dabbf998f618f Reviewed-on: https://gem5-review.googlesource.com/c/16522 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-19sim: Add a mechanism to exit the simulation loop immediately.Gabe Black
There are some cases, specifically when running systemc, that it's necessary to exit the simulation loop immediately rather than finishing running events scheduled for the current Tick. When running under sc_main, sc_stop and sc_pause return control to sc_main which can happen immediately. When running without sc_main, control needs to return to the python config script which needs to happen through a global exit event. Since sc_pause and sc_stop are supposed to stop simulation without necessarily letting all the events at the current time run, we need a way to schedule an exit event with a very high priority (rather than a very low priority). This change adds a new exitSimLoopNow function which does that, and adds a new constructor to the GlobalSimLoopExitEvent which uses that priority. Also, a couple of cruft functions from the sim events are removed. Change-Id: Icfbec17fb10f98084a75740acd839dbf4096fbb3 Reviewed-on: https://gem5-review.googlesource.com/c/16444 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-19cpu: Add ISA* getter in Thread interfaceGiacomo Gabrielli
This patch is adding a ISA* getter to the TC interface Change-Id: Ib8ddc5d8fdd44e782f50a2ad15878a6bcf931e58 Reviewed-on: https://gem5-review.googlesource.com/c/16462 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-02-18arch-generic: Making base TLB class a MemObjectIvan Pizarro
Allow configuring a TLB hierarchy using ports Change-Id: I1f791829d4e072a9104e67eacf69a69de9543634 Reviewed-on: https://gem5-review.googlesource.com/c/14117 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-18arch-arm: Move GICv3 detection at startup timeGiacomo Travaglini
At the moment the haveGicV3 parameter is used only to signal its presence when reading the MISCREG_ID_AA64PFR0_EL1 register. It depends on the system->getGIC pointing to a GICv3 model. However this pointer is set in the System only at init time (after construction), which means that the haveGICv3CPUInterface will always be false. This patch is fixing this by moving the parameter initialization at startup time, together with the cpu interface registration. Change-Id: I8da6711ea741ecd0f78ec8ca60a8c3ae3bca2421 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16483 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-18dev-arm: LPI support for GICv3. This doesn't include an ITS model.Jairo Balart
Change-Id: Ia2c02cca4f95672d6361fba16201a56e2047ddb7 Reviewed-on: https://gem5-review.googlesource.com/c/16142 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-18base: Fix enums checkpointingGiacomo Travaglini
Creating an extra version of string to number converters (__to_number) in base/str.hh; it will be used by enums only when unserializing them. The reason not to have a single helper for both enums and integers is that std::numeric_limits trait is not specialized for enums. We fix this by using the std::underlying_type trait. Change-Id: I819e35c0df8c094de7b7a6390152964fa47d513d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16382 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-15cpu: Fix fast build broken due to unused variableGiacomo Travaglini
This fixes fast build for commit 25dc765889d948693995cfa622f001aa94b5364b (fast build is striping out assertions) Change-Id: I9536ad58a3d85990b16a1f8c2515f6bf5d3acf71 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16463 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-14systemc: Add a systemc_home directory which maps to the ext headers.Gabe Black
Some systemc code bases expect to find a SYSTEMC_HOME environment variable which points to the installed header files provided by systemc, all under ${SYSTEMC_HOME}/include. The systemc headers in gem5 are not supposed to be installed anywhere, but to satisfy those expectations this change creates a dummy systemc_home directory with an include/ in it which has headers which just include the actual headers in src/systemc/ext. More gem5 aware code bases can still access the headers either by letting gem5's scons environment -I the ext directory, or can do so themselves if they're not being built by gem5's scons. Change-Id: I5f2e6bfcf20dd314d525207c2e13ca53474a33f3 Reviewed-on: https://gem5-review.googlesource.com/c/16263 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-14systemc: Make an include in src/systemc/ext use a relative path.Gabe Black
The includes in src/systemc/ext are supposed to use relative paths so that they can be included in other bodies of code which aren't based in gem5 and don't share it's -I-s, or potentially even have access to anything outside of src/systemc/ext. Change-Id: Icde457329c2c4ab4689221015bfcfe2ff8b051f0 Reviewed-on: https://gem5-review.googlesource.com/c/16262 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-13cpu: Added 8KB and 64KB TAGE-SC-L branch predictorJavier Bueno
The original paper of the branch predictor can be found here: http://www.jilp.org/cbp2016/paper/AndreSeznecLimited.pdf Change-Id: I684863752407685adaacedebb699205c3559c528 Reviewed-on: https://gem5-review.googlesource.com/c/14855 Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-13python: Remove uses of tuple unpacking in function paramsAndreas Sandberg
Python 3 doesn't support tuple unpacking in function parameters and lambdas. Change-Id: I36c72962e33a9ad37145089687834becccc76adb Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15991 Reviewed-by: Gabe Black <gabeblack@google.com>
2019-02-13python: Replace deprecated repr syntaxAndreas Sandberg
Change-Id: I5f9538cf2ca5ee17c51e7c5388d3aef363fcfa54 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15989 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-13python: Switch from using compare to key in list sortAndreas Sandberg
Python 3 has deprecated the use of a comparison function in favour of a key extraction function. Change-Id: I4b7eab791ecbdfbf7147f57fdbc7cbe8f1de20dd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15995 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-13sim-se: update the arm kernel versionAyaz Akram
This change is needed to run cpu tests with ARM binaries compiled with newer linux kernel headers Change-Id: I6cbf132c38d4b18f971ee32272ddb6a5a791a625 Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15855 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-12python: Replace dict.has_key with 'key in dict'Andreas Sandberg
Python 3 has removed dict.has_key in favour of 'key in dict'. Change-Id: I9852a5f57d672bea815308eb647a0ce45624fad5 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15987 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-12python: Add missing defines importAndreas Sandberg
The _check_tracing helper function in main.py depends on defines to check if tracing has been enabled at compile time. This module is imported in main() but not at the module level, which breaks this function. Change-Id: I26d65a4320da8618e0e552553695884fd2c880e0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16402 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-12python: Replace DictMixin with Mapping / MutableMappingAndreas Sandberg
Python 3 has removed support for DictMixin, so switch to Mapping / MutableMapping in collections which provides the same functionality. Change-Id: I61fbe366d2c9fc6e01b470f82f49cc02b99dec32 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15984 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-02-12python: Replace orderdict with collections.OrderedDictAndreas Sandberg
Python 2.7 and newer has support for ordered dictionaries in the standard library. Remove this custom class. Change-Id: I4b720405aa3c4ce8d5c0b401eefe744a85ac3a3e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16362 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-02-12python: Update use of exec to work with Python 3Andreas Sandberg
Python 3 uses 'exec(code, globals)' instead of 'exec code in globals'. Switch to the newer syntax since it is supported by Python 2.7. Also, move check_tracing out of main to work around a bug in Python 2.7. Change-Id: I6d390160f58783e1b038a572b64cdf3ff09535fa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15986 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-02-12python: Switch to using open instead of fileAndreas Sandberg
Python 3 doesn't support the file(name, mode) syntax which has been deprecated in favour of open. Change-Id: I35ef8690d97a5243860a64ff985fd22fa86253f1 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15985 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-12mem-cache: Irregular Stream Buffer PrefetcherJavier Bueno
Based in the description of the following publication: Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses for improved correlated prefetching. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM, New York, NY, USA, 247-259. Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 Reviewed-on: https://gem5-review.googlesource.com/c/15215 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2019-02-12mem-cache: Added the Delta Correlating Prediction Tables PrefetcherJavier Bueno
Reference: Multi-level hardware prefetching using low complexity delta correlating prediction tables with partial matching. Marius Grannaes, Magnus Jahre, and Lasse Natvig. 2010. In Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers (HiPEAC'10) Change-Id: I7b5d7ede9284862a427cfd5693a47652a69ed49d Reviewed-on: https://gem5-review.googlesource.com/c/16062 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
The importer in Python 3 doesn't like the way we import SimObjects from the global namespace. Convert the existing SimObject declarations to import from m5.objects. As a side-effect, this makes these files consistent with configuration files. Change-Id: I11153502b430822130722839e1fa767b82a027aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15981 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-12arch-mips: Remove unused Python fileAndreas Sandberg
Change-Id: I7155915fccdec1d9f116f2a8617474188a91165b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16302 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-12python: Make exception handling Python 3 safeAndreas Sandberg
Change-Id: I9c2cdfad20deb1ddfa224320cf93f2105d126652 Reviewed-on: https://gem5-review.googlesource.com/c/15980 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-12python: Fix native module initialisation on Python 3Andreas Sandberg
The approach we currently use to register our native modules doesn't work on Python 3. Convert the code to use the Python inittab instead of the old ad-hoc method. Change-Id: I961f8a33993c621473732faeaab955a882769a4b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15979 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com>
2019-02-12mem-ruby: Fixing TopologyPouya Fotouhi
The constructor assumes the number of nodes (i.e. controllers) equal to the number of external nodes. This is a not necessarily valid for all cases (e.g MESI_Three_Level - where L0s are directly connected to L1s). MachineType_base_number(MachineType_NUM) provides the total number of controllers. Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Change-Id: Id906099dc967ec70aa34dedb0b55351031ff242c Reviewed-on: https://gem5-review.googlesource.com/c/15716 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-12mem-ruby: Fixing MESI Three LevelPouya Fotouhi
Adding back some changes done in patch 676ae57827. Transient state IS_I, STALE_DATA, Data_Stale event are necessary. Issue: (cacheline A, initial state for P0 and P1 is I) | P0 | P1 | |GETX (A)| | | |GETS (A)| |Inv_All | | P1 never sends the ACK - deadlock It should ACK, later upon data use it as stale data, and got to I. Solution: P1(A): GETS: I->IS Inv_All: IS->IS_I, Send ACK Data: IS_I->I, STALE_DATA to L0 Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Change-Id: I1e7b2c05439d08579c68d8eb444e0f332e75e07f Reviewed-on: https://gem5-review.googlesource.com/c/15715 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-11systemc: Change the type of a loop counter to avoid a warning.Gabe Black
g++ complained about comparing an signed int loop counter with the return value of a size() function. This change changes it to an unsigned to make g++ happy/quiet. Change-Id: I28fa79c448465b24d77b5623860f9b991f313561 Reviewed-on: https://gem5-review.googlesource.com/c/16286 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-11scons: Change an = to a += when accumulating sources from filters.Gabe Black
The loop accidentally used a = when it should have used a +=, meaning only the sources from the final filter would be used. Change-Id: Ie066a5f85696f05d9ad3cf61f928b12deb39475b Reviewed-on: https://gem5-review.googlesource.com/c/16285 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-11systemc: scons: Specify RPATH as a list.Gabe Black
scons will attempt to use insert() on the value of RPATH when adding in additional values. That will fail if RPATH is a Literal. Change-Id: I9da75c6b189f12843a3452cdf92f7b56c0ec340b Reviewed-on: https://gem5-review.googlesource.com/c/16284 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-08cpu: Proposal for changing the indirect branch predictor interfaceJairo Balart
Now the indirect branch predictor handles its own GHR instead of getting the one from the direction predictor. Also, now the commit method of the indirect predictor is called for every pending branch on an update, as the indirect predictors may want to update their interal structures/histories with the information of each branch. Change-Id: I7053fbea42a53960a3bc1ba32912cc99c160511e Reviewed-on: https://gem5-review.googlesource.com/c/15318 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-08riscv: fix AMO, LR and SC instructionsTuan Ta
(1) Atomic Memory Operation (AMO) This patch changes how RISC-V AMO instructions are implemented. For each AMO, instead of issuing a locking load and an unlocking store request to downstream memory system, this patch issues a single memory request that contains a corresponding AtomicOpFunctor to the memory system. Once the memory system receives the request, the atomic operation is executed in one single step. This patch also changes how AMO instructions handle acquire and release flags in AMOs (e.g., amoadd.aq and amoadd.rl). If an AMO is associated with an acquire flag, a memory fence is inserted after the AMO completes as a micro-op. If an AMO is associated with a release flag, another memory fence is inserted before the AMO executes. If both flags are specified, the AMO is broken down into a sequence of 3 micro-ops: mem fence -> atomic RMW -> mem fence. This change makes this AMO implementation comply to the release consistency model. (2) Load-Reserved (LR) and Store-Conditional (SC) Addresses locked by LR instructions are tracked in a stack data structure. LR instruction pushes its target address to the stack, and SC instruction pops the top address from the stack. As specified by RISC-V ISA, a SC fails if its target address does not match with the most recent LR. Previously, there was a single stack for all hardware thread contexts. A shared stack between thread contexts can lead to a infinite sequence of failed SCs if LRs from other threads keep pushing new addresses to this stack. This patch gives each context its private stack to address the problem. This patch also adds extra memory fence micro-ops to lr/sc to guarantee a correct execution order of memory instructions with respect to release consistency model. Change-Id: I1e95900367c89dd866ba872a5203f63359ac51ae Reviewed-on: https://gem5-review.googlesource.com/c/8189 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2019-02-08cpu: support atomic memory request type with AtomicOpFunctorTuan Ta
This patch enables all 4 CPU models (AtomicSimpleCPU, TimingSimpleCPU, MinorCPU and DerivO3CPU) to issue atomic memory (AMO) requests to memory system. Atomic memory instruction is treated as a special store instruction in all CPU models. In simple CPUs, an AMO request with an associated AtomicOpFunctor is simply sent to L1 dcache. In MinorCPU, an AMO request bypasses store buffer and waits for any conflicting store request(s) currently in the store buffer to retire before the AMO request is sent to the cache. AMO requests are not buffered in the store buffer, so their effects appear immediately in the cache. In DerivO3CPU, an AMO request is inserted in the store buffer so that it is delivered to the cache only after all previous stores are issued to the cache. Data forwarding between between an outstanding AMO in the store buffer and a subsequent load is not allowed since the AMO request does not hold valid data until it's executed in the cache. This implementation assumes that a target ISA implementation must insert enough memory fences as micro-ops around an atomic instruction to enforce a correct order of memory instructions with respect to its memory consistency model. Without extra memory fences, this implementation can allow AMOs and other memory instructions that do not conflict (i.e., not target the same address) to reorder. This implementation also assumes that atomic instructions execute within a cache line boundary since the cache for now is not able to execute an operation on two different cache lines in one single step. Therefore, ISAs like x86 that require multi-cache-line atomic instructions need to either use a pair of locking load and unlocking store or change the cache implementation to guarantee the atomicity of an atomic instruction. Change-Id: Ib8a7c81868ac05b98d73afc7d16eb88486f8cf9a Reviewed-on: https://gem5-review.googlesource.com/c/8188 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-08kern,sim: implement FUTEX_WAKE_OPMoyang Wang
This patch implements FUTEX_WAKE_OP operation in the futex syscall. Below is its description: int futex(int *uaddr, int futex_op, int val, const struct timespec *timeout, int *uaddr2, int val3); This operation was added to support some user-space use cases where more than one futex must be handled at the same time. The most notable example is the implementation of pthread_cond_signal(3), which requires operations on two futexes, the one used to implement the mutex and the one used in the implementation of the wait queue associated with the condition variable. FUTEX_WAKE_OP allows such cases to be implemented without leading to high rates of contention and context switching. Reference: http://man7.org/linux/man-pages/man2/futex.2.html Change-Id: I215f3c2a7bdc6374e5dfe06ee721c76933a10f2d Reviewed-on: https://gem5-review.googlesource.com/c/9630 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-08sim, kern: support FUTEX_CMP_REQUEUEMoyang Wang
This patch supports FUTEX_CMP_REQUEUE operation. Below is its description from Linux man page: futex syscall: int futex(int *uaddr, int futex_op, int val, const struct timespec *timeout, int *uaddr2, int val3); This operation first checks whether the location uaddr still contains the value val3. If not, the operation fails with the error EAGAIN. Otherwise, the operation wakes up a maximum of val waiters that are waiting on the futex at uaddr. If there are more than val waiters, then the remaining waiters are removed from the wait queue of the source futex at uaddr and added to the wait queue of the target futex at uaddr2. The val2 argument specifies an upper limit on the number of waiters that are requeued to the futex at uaddr2. Reference: http://man7.org/linux/man-pages/man2/futex.2.html Change-Id: I6d2ebd19a935b656d19d8342f7ab450c0d2031f4 Reviewed-on: https://gem5-review.googlesource.com/c/9629 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-02-08sim: handle the case when there're not enough HW thread contextsTuan Ta
In SE mode, since there's no OS scheduler, the number of active SW threads is limited by the number of HW thread contexts. Previously, if there is no spare HW thread context, the simulator just fails and stops. Instead, this patch returns EAGAIN error code from a clone syscall if there's no available HW thread context. Then it's up to the simulated program to handle the error. Linux man page reference: http://man7.org/linux/man-pages/man2/clone.2.html http://man7.org/linux/man-pages/man2/fork.2.html Change-Id: Ib4e092433e49de4dde376c8cb81f7d3f7851cbc0 Reviewed-on: https://gem5-review.googlesource.com/c/9628 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-02-08riscv: fixed syscall return valueTuan Ta
In case of failure, a syscall returns a negative value encoding the error code. This patch makes the risc-v implementation returns the encoded value instead of its absolute value upon a failure of a syscall. Change-Id: I6032b0337fe1cff5b326dbc6bb3b87a415f03300 Reviewed-on: https://gem5-review.googlesource.com/c/9627 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2019-02-08cpu: fix how branching is handled when a thread is suspended in MinorCPUTuan Ta
When a thread is suspended, all instructions after the suspension need to be discarded since the thread will take a different execution stream when it wakes up. To do that, in MinorCPU, whenever a thread gets suspended, we change the current execution stream by updating the current branch with BranchData::SuspendThread reason. Change-Id: I7cdcda22c1cf6e8ac8db8800b7d9ec052433fdf3 Reviewed-on: https://gem5-review.googlesource.com/c/9626 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-08cpu: stop scheduling suspended threads in all stages of MinorCPUTuan Ta
This patch makes suspended threads non-schedulable in Fetch1, Fetch2, Decode and Execute stages in MinorCPU. Change-Id: Ie79857e13b7b782d9c58c32310993a132b609cf9 Reviewed-on: https://gem5-review.googlesource.com/c/9625 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-08riscv: ignore nanosleep syscallTuan Ta
Change-Id: I564a09564da668a5db3e75f15b33efaca363d71a Reviewed-on: https://gem5-review.googlesource.com/c/9624 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-08sim,cpu: make exit_group halt all threads in a groupTuan Ta
When a thread calls exit_group, in addition to halting the thread itself, it needs to halt all other threads in its group (i.e., threads sharing the same thread group ID). This patch enables threads to do that. Change-Id: Ib2e158fb27cf98843f177a64a2d643b1bbc94d03 Reviewed-on: https://gem5-review.googlesource.com/c/9623 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-08arch-riscv: initialize RISC-V's thread pointer register in clone syscallTuan Ta
This patch initializes thread pointer register to Thread Local Storage (TLS)'s pointer given to a clone system call. Change-Id: I03e2cf4763e6a0ed31f357772a513a05e1e3461b Reviewed-on: https://gem5-review.googlesource.com/c/9622 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-02-08sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET opsTuan Ta
This patch adds support for two operations in futex system call: FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET. The two operations are used to selectively wake up a certain thread waiting on a futex variable. Basically each thread waiting on a futex variable is associated with a bitset that is checked when another thread tries to wake up all threads waiting on the futex variable. Change-Id: I2300e53b144d8fae226423fa2efb0238c1d93ef9 Reviewed-on: https://gem5-review.googlesource.com/c/9621 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-02-08cpu: fixed how O3 CPU executes an exit system callTuan Ta
When a thread executed an exit syscall in SE mode, the thread context was removed immediately in the same cycle, which left inflight squash operations and trap event incomplete. The problem happened when a new thread was assigned to the CPU later. The new thread started with some incomplete transactions of the previous thread (e.g., squashing). This problem could cause incorrect execution flow for the new thread (i.e., pc was not reset properly at the exit point), deadlock (i.e., some stage-to-stage signals were not reset) and incorrect rename map between logical and physical registers. This patch adds a new state called 'Halting' to the thread context and defers removing thread context from a CPU until a trap event initiated by an exit syscall execution is processed. This patch also makes sure that the removal of a thread context happens after all inflight transactions of the to-be-removed thread in the pipeline complete. Change-Id: If7ef1462fb8864e22b45371ee7ae67e2a5ad38b8 Reviewed-on: https://gem5-review.googlesource.com/c/8184 Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-08arch-arm: Fix Virtual interrupts in AArch64Giacomo Travaglini
Checking if cpsr.mode is equal to MODE_HYP doesn't work for AArch64. This is because AArch64 is using different modes when in EL2, like EL2T and EL2H. This made Virtual Interrupts to be triggered even when executing in EL2 (hypervisor) whereas they should interrupt the scheduled VM only (Non-Secure EL0 and EL1). This patch is fixing this by using the generic currEL() helper for getting the exception level, which is working for both AArch32 and AArch64. Change-Id: I08640050ef06261f280ba1e63ca9f32c805af845 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16202 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-08arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30Giacomo Travaglini
Change-Id: I649f8507ccb6c814b46b0b9b7e39dc912ecd9006 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16242
2019-02-08arch-arm: Allow ArmPPI usage for PMUGiacomo Travaglini
Differently from ArmSPIs, ArmPPI interrupts need to be instantiated by giving a ThreadContext pointer in the ArmPPIGen::get() method. Since the PMU is registering the ThreadContext only at ISA startup time, ArmPPI generation in deferred until the PMU has a non NULL pointer. Change-Id: I17daa6f0e355363b8778d707b440cab9f75aaea2 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16204 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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