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2019-04-30arch: cpu: Track kernel stats using the base ISA agnostic type.Gabe Black
Then cast to the ISA specific type when necessary. This removes (mostly) an ISA specific aspect to some of the interfaces. The ISA specific version of the kernel stats still needs to be constructed and stored in a few places which means that kernel_stats.hh still needs to be a switching arch header, for instance. In the future, I'd like to make the kernel its own object like the Process objects in SE mode, and then it would be able to instantiate and maintain its own stats. Change-Id: I8309d49019124f6bea1482aaea5b5b34e8c97433 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18429 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-30alpha: Implement HWREI in the ISA.Gabe Black
This moves it out of generic interfaces and the CPU implementations. Change-Id: I6767d6b26d0ae128b5bdad5830dce838be74e256 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18431 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30alpha: Add some control registers to the ISA operands list.Gabe Black
These will be used in the in-ISA HWREI implementation. Change-Id: Ia9f7bf1aa2dbd764c878911c2cba680840397c62 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18430 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30sim-se: add socket ioctlsBrandon Potter
The OpenMPI 1.8.2 runtime needs the ioctl code included in this patch to issue socket operations on the host machine. Change-Id: I687b31f375a846f0bab2debd9b9472605a4d2c7d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12123 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-30systemc: Add a distinct async_request_update mechanism.Gabe Black
This mechanism had just been plumbed into the regular request_update, but that doesn't have any thread safety which is the whole point of async_request_update. This new mechanism puts async update requests into their own list which is checked any time normal updates happen. The delta cycle which triggers those updates must happen through some other means which will usually be ok. The exact timing of the update is undefined, so it would be legal for it to either not be recognized before the impending end of the simulation, or for it to get picked up by subsequent activity. If there isn't subsequent activity but the simulation also doesn't end, for instance if there are only gem5 events left, then that update could be lost. That is an unresolved issue. It would be nice to schedule a "ready" event if async updates were added which would ensure they wouldn't starve. Unfortunately that requires the event queue lock, and in practice it's been found that a systemc process might block, effectively holding the event queue lock, while it waits for some asyncrhonous update to give it something to do. This effectively deadlocks the system since the update is blocked on the lock the main thread holds, and the main thread is blocked waiting for the update. Change-Id: I580303db01673faafc2e63545b6a69b3327a521c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18288 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-29cpu: Get rid of the (read|set)RegOtherThread methods.Gabe Black
These are implemented by MIPS internally now. Change-Id: If7465e1666e51e1314968efb56a5a814e62ee2d1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18436 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-29mips: Implement readRegOtherThread and setRegOtherThread directly.Gabe Black
These accessors can be implemented as helper functions within MIPS without having to plumb them through a bunch of common interfaces. There are a few problems with the way they were implemented which are carried forward to this new implementation as well. That includes hiding the register accesses from the ISA parser and therefore the CPU's dependency tracking, potentially panicing or accessing a non existent thread based on a possible set of input values, and modifying register values even if an instruction is being executed speculatively. Fixing these problems would be fairly involved and require changing how dependencies are tracked in all the CPUs so that they can act across threads, and also how registers are handled in the ISA description itself. The original implementation just punted on making this work in CPUs other than the minor CPU (and potentially one or more CPU models that were not and/or are not in the code base). Where as that implementation might have paniced if these methods were called, this will attempt to work, but may have incorrect behavior based on the limitations described above. I'd consider this an acceptable tradeoff, at least for the time being. Change-Id: I94adceafb9812a8641c76ea3518c3285c31baf51 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18435 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-29cpu: Include debug flags regardless of whether the ISA is null.Gabe Black
Whether debug flags are available has no interaction with what the ISA is. Change-Id: I71d9204f948618831796e6c7a4c16bbebfb1a4fb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18428 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-29sim-se: create Proc out files in out dirSteve Reinhardt
Redirected output files from Process objects were being created in the current directory instead of in the output directory. Change-Id: Ieb6ab5556fbcc811f4f24910da247d4dcdbc71bd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12122 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-29arch-arm: Faults DebugFlag now printing inst opcode if availableGiacomo Travaglini
This makes it easier to debug unimplemented instructions. Change-Id: Iaaa288037326722f07251299fd68eacb2e295376 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18396 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-29arch-arm: Report real instruction encoding when UndefinedGiacomo Travaglini
When dumping the opcode that caused an Undefined Instruction, we just want to dump the real instruction encoding, and not the extended version with metabits (like thumb, bigThumb etc). This was not appening when panicking in SE mode. The patch is also replacing custom masking in the Unknown(64) disassembler in favour of ArmStaticInstruction::encoding() helper. Change-Id: I9eb6fd145d02b4b07bb51f0bd89ca014d6d5a6de Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18395 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-28arch, sim: Simplify the AuxVector type.Gabe Black
The AuxVector type has a bunch of accessors which just give access to the underlying variables through references. We might as well just make those members accessible directly. Also, the AuxVector doesn't need to handle endianness flips itself. We can tell the byteswap mechanism how to flip an AuxVector, and let it handle that for us. This gets rid of the entire .cc file which was complicated by trying to both hide the ISA specific endianness translations, and instantiate templated functions in a .cc. Change-Id: I433cd61e73e0b067b6d628fba31be4a4ec1c4cf0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18373 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-28mem: Remove the ISA specialized versions of port proxy's read/write.Gabe Black
These selected their behavior based on ifdefs and had to be disabled when on the NULL ISA. The versions which take an explicit endianness have been renamed to just read/write instead of readGtoH and writeHtoG since the direction of the translation is obvious from context. Change-Id: I6cfbfda6c4481962d442d3370534e50532d41814 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18372 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-28mem: Minimize the use of MemObject.Gabe Black
MemObject doesn't provide anything beyond its base ClockedObject any more, so this change removes it from most inheritance hierarchies. Occasionally MemObject is replaced with SimObject when I was fairly confident that the extra functionality of ClockedObject wasn't needed. Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-04-27python: Get rid of the VectorPort constructor.Gabe Black
The only thing it was doing beyond calling the parent Port __init__ was to set isVec, and nobody actually looks at that value later. Change-Id: I567cb583e6f02a6c18504b9bb20dd13b3c934822 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18175 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-27python: Replace the Master/Slave Ports with Request/Response ports.Gabe Black
These are a little more descriptive and a little less potentially offensive. Change-Id: I84c30f783f0a4c242cb4f54ab272b6fdf1e9eec7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18174 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-26arch-arm: updateMiscReg not setting isHyp in aarch64Giacomo Travaglini
The isHyp flag should be set for a TLB::NormalTran when in EL2. This was happening in aarch32 only, where the CPSR mode is checked, while aarch64 was only using it for explicit EL2 translations, like for AT instructions. Change-Id: I54605811e9dde75b5cf8868190b0f4c2a8d46570 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18394 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-26arm: Factor some repetition out of the ProcessInfo constructor.Gabe Black
Change-Id: I34f952d1097886704d37304478de125a915b2615 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18371 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-25arm: Fix some style issues in stacktrace.cc.Gabe Black
De-indent the ArmISA namespace, and wrap some overly long lines. Change-Id: Idc02b025bdfda483ddbd27d662e2314a5cbcb23c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18370 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-25x86: Refactor the ProcessInfo constructor.Gabe Black
That function had a lot of repetition which is easily factored out into its own function. Change-Id: I3b7a522de2ba808856bb59df75b80efde6780e3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18369 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-25x86: Fix some style issues in stacktrace.cc.Gabe Black
De-indent the X86ISA namespace, and wrap some overly long lines. Change-Id: I01a6b66a1cf721e16e4ed4dd1c3469ee112e9177 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18368 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25sim-se: add a faux-filesystemDavid Hashe
This change introduces the concept of a faux-filesystem. The faux-filesystem creates a directory structure in m5out (or whatever output dir the user specifies) where system calls may be redirected. This is useful to avoid non-determinism when reading files with varying path names (e.g., variations from run-to-run if the simulation is scheduled on a cluster where paths may change). Also, this changeset allows circumventing host pseudofiles which have information specific to the host processor (such as cache hierarchy or processor information). Bypassing host pseudofiles can be useful when executing runtimes in the absence of an operating system kernel since runtimes may try to query standard files (i.e. /proc or /sys) which are not relevant to an application executing in syscall emulation mode. Change-Id: I90821b3b403168b904a662fa98b85def1628621c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12119 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25arch-arm: Remove un-needed hyp flag in TLBI operationsGiacomo Travaglini
The hyp flag was probably a legacy pre-v8 flag distinguishing invalidation targeting PL2 translation regime (hyp mode). Since the introduction of target_el parameter, hyp boolean is not needed anymore. The patch works by setting the hyp flag in the flush* methods in the TLB automatically by checking if target_el == EL2. Change-Id: I798009e09ff24a383dea871e348188bae2685e8e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18389 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25arch-arm: Correct target EL field in TLBI operationsGiacomo Travaglini
Some TLB Invalidation operations affecting the EL2 translation regime were marked as targeting EL1 instead of EL2 Change-Id: I77821eec7a409e9df6a6814855f9a375832ffe74 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18388 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25dev-arm: Move GICv3 (Re)Ditributor address in Realview.pyGiacomo Travaglini
Base addresses for GICv3's Distributor and Redistributors are implementation defined: they depend on the platform rather than the model. This patch is then moving dist_addr and redist_addr initialization in Realview.py Change-Id: I1246df500262f4d3d5a38e62d0240945f90941ee Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18393 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25dev-arm: Limit number of max PE in GICv3 to 128Giacomo Travaglini
This is needed since there is a problem in the memory layout of VExpress_GEM5_V2 as it is: having 256KB pages is creating overlapping regions when reserving space for 256 PEs. GICv3 redistributors: 0x2c010000 - 0x30010000 PCI regions: 0x30000000 - 0x40000000 We fix this by cutting down the number of supported PEs to 128 Change-Id: I6e87f66a6150a441ccba298662b4548a4972dc40 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18392 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25dev-arm: Add GICv4 extension switch in GICv3Giacomo Travaglini
This is currently used only for determining which is the correct size of redistributors in memory (256KB in GICv4 and 128KB in GICv3) Change-Id: I2c07005e97167fde03548313c9927176788f31dd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18391 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25dev-arm: Check for maximum number of supported PE in GICv3Giacomo Travaglini
This is currently set to 256 Change-Id: If7bb2847c22f29bfa0cb4ebf4a7984ee43ab4e29 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18390 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-24cpu,mem: missing override specifierAndrea Mondelli
Change-Id: I731d3ef021596450ac307461f215760a148bb28a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18348 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-24systemc: Use the new TLM socket types in the TLM bridge SimObjects.Gabe Black
These are in the definition of the python version of the SimObjects. Change-Id: Iadb143158815df68cf32cc254ad19f755ab4e78a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18173 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-04-24systemc: Add Port types for initiator and target sockets.Gabe Black
These make it clear that a port represents a TLM socket, what direction it faces, and what its width is. Change-Id: Idcbea2b9b053f1e0685e011bc2c7de2468fb25b2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18172 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-04-24dev: Use the new Port role mechanism to make an EtherInt Port type.Gabe Black
This type always uses the same "ETHERNET" role, and all connections are symmetric and self compatible. Change-Id: I1d060f8c098d52ae9f65c052f816bc813590ff9c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18171 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-24python: Generalize the Port.splice function.Gabe Black
Now that the MASTER and SLAVE roles aren't special, the splice function needs to be able to handle arbitrarily role-d peers. Change-Id: I22a28b7cdcb93f7f370730b7e38b0e6d3500a6a0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18170 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-24python: Generalize the dot_writer to handle non Master/Slave roles.Gabe Black
Change-Id: I6d93c28e754c0cacacdd5e8885c45bc861135e94 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18169 Maintainer: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-24python: Make Port roles a more generic concept.Gabe Black
A recent change got rid of the strict Master => Slave port relationship which used to be checked in python and instead left the checking up to C++. One major downside to this approach is that it was no longer obvious in the configuration what was supposed to be connected to what, and it still left the arbitrary and misleading MasterPort and SlavePort types in the Ethernet devices which could now connect with each other symmetrically but couldn't actually connect to an arbitrary MasterPort/SlavePort. This change exposes the base Port and VectorPort types, and makes them accept a "role" parameter in __init__ which used to be set directly by their subclasses. This role can be any string, and will be used later to check for compatiblity and to give a hint as to what can be connected to what in the SimObject definitions. To make the checks work with arbitrary compatible pairs, the base Port type now has a class method called compat() which accepts a pair of roles which will become mutually compatible, ie any port with the first role will be allowed to connect to any port with the second role, and vice versa. To be self compatible, the same role should be passed in for both parameters. To maintain compatibility, the MasterPort and SlavePort types are retained, but now they're nothing special and could have been set up in any arbitrary SimObject .py file. The same is true for MasterVectorPort and SlaveVectorPort. Also, since we can no longer assume that all edges in the dot graph of the config should start with a port with the MASTER role and end with a port with the SLAVE role, Ports now track an is_source property which says whether the arrow head should be surpressed at that end of the edge representing the connection. Change-Id: Ifcc6faab05e437ad87cd21f0ba613b09cf21c321 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18168 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-04-23python: fix tracing after Python 3 refactorCiro Santilli
gem5.opt --debug-flags ExecAll was failing with: ImportError: No module named defines on Python 2. Change-Id: I06959d6e0ccb7c661c7c749af3392632dac779f3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18108 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-22sim-se: Enhance clone for X86KvmCPUAlexandru Dutu
This changeset enables clone to work with X86KvmCPU model, which will allow running multi-threaded applications at near hardware speeds. Even though the application is multi-threaded, the KvmCPU model uses one event queue, therefore, only one hardware thread will be used, through KVM, to simulate multiple application threads. Change-Id: I2b2a7b1edb1c56eeb9c4fa0553cd236029cd53f8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18268 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-22mem-cache: Fix fix of replacement countDaniel
Commit 7976b561de61b7523ca9a860154ad7ba701d12a7 tried fixing replacement update when a single location can be associated to multiple blocks. Although the comment of the correct action was added, the proper validation check was forgotten. This change adds that check and moves doing the eviction to when there is a valid block. Change-Id: I31d8bb914ccfd1849e9d97464d70a58a62f59533 Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18210 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-22cpu: Eliminate the ProxyThreadContext class.Gabe Black
Replace it with direct inheritance from the ThreadContext class in the SimpleThread class which was the only place it was used. Also take the opportunity to use some specialized types instead of ints, etc., add some consts, and fix some style issues. Change-Id: I5d2cfa87b20dc43615e33e6755c9d016564e9c0e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18048 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-19mem-cache: Fix increasing replacement countDaniel R. Carvalho
Replacements should be increased when there is any evicted block, which does not necessarily have to be the victim. For example, assume a superblock contains 4 blocks, and both A and C are stored compressed (belonging to SB_1). Then F, from SB2 needs to make room by replacing SB1. If F map to location 2, the number of replacements should be increased, even though 2 had no valid blocks: Tag Data Tag Data |SB_1|--|A|X|C|X| --> |SB_2| |X|F|X|X| 1 2 3 4 1 2 3 4 Change-Id: I7b3735d28a35faa8d8fa613a1555bb258da65859 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18208 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-19mem-cache: Remove blk_addr from Queue::trySatisfyFunctionalDaniel R. Carvalho
The blk_addr is pkt->getBlockAddr(), and therefore can be acquired internally, when needed, as long as the pkt is provided. Change-Id: I2780445d2a0cb9e27257961efc4f438cc19550e5 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17537 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-19mem-cache: Add match functions to QueueEntryDaniel R. Carvalho
Having the caller decide the matching logic is error-prone, and frequently ends up with the secure bit being forgotten. This change adds matching functions to the QueueEntry to avoid this problem. As a side effect the signature of findPending has been changed. Change-Id: I6e494a821c1e6e841ab103ec69632c0e1b269a08 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17530 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-19mem: Add packet matching functionsDaniel R. Carvalho
Add both block and non-block-aligned packet matching functions, so that both address and secure bits are checked when checking whether a packet matches a request. Change-Id: Id0069befb925d112e06f250741cb47d9dfa249cc Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17533 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-19mem-cache: Move Target to QueueEntryDaniel R. Carvalho
WriteQueueEntry's target has 100% functionality overlap with MSHR's, therefore make it base to MSHR::Target. Change-Id: I48614e78179d708bd91bbe75a752e5a05146e8eb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17534 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-19mem-cache: Assert Entry inherits from QueueEntry in QueueDaniel R. Carvalho
Queue has several assumptions regarding its template parameter, so make sure they are fulfilled by forcing Entry to be derived from QueueEntry. Change-Id: I0203a62aec00c04ac89e9674d86a44a07f9f13ab Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17529 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-19mem: Make DRAMCtrl::decodeAddr constDaniel R. Carvalho
DRAMCtrl's decodeAddr does not need to modify the packet it receives, nor should it modify the contents of the class, and therefore both the packet and the function are made const. Change-Id: I577f48d9a43611ba54878a9a793cb7b4fbb326f4 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17540 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-19mem: Allow packet to provide its own addr rangeDaniel R. Carvalho
Add a getter to Packet to allow it to provide its own addr range. Change-Id: I2128ea3b71906502d10d9376b050a62407defd23 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17536 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-16mem: missing override specifierAndrea Mondelli
Change-Id: Ied4817bcda317826303a1bb688b41823b18b489b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18128 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-14mem: Teach SimpleMem to return a MemBackdoor when appropriate.Gabe Black
If the back door SimpleMem inherits from AbstractMem has a pointer and is hence valid, SimpleMem will return that pointer when asked. Change-Id: I734daba48e4ae5b4ad8ac9a108e7b12b5e82803f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17669 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-14mem: Maintain a back door into the AbstractMem's backing store.Gabe Black
The backing store pointer is added to the back door when it's set, assuming that the range isn't interleaved. If it is interleaved, then there isn't a way to get a flat pointer to the backing store. Depending on how the backing store is set up, it may be possible to return a larger backdoor which applies to all interleaved memories at the same time and to avoid problems with interleaving. I'm leaving this as a todo. Change-Id: I0e531c22835ec10954ab39f761b3d87666b59220 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17668 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
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