summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2019-12-03fastmodel: Suppress a spurious warning on clang for amba_pv.h.Gabe Black
This header comes from the fast model distribution and so we can't (easily) disable the warning locally. Change-Id: I2c1eee48f8970bb17466f0759f0077a5d45e76af Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23123 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-01arch-riscv: Fix disassembling of immediate for c.lui instructionIan Jiang
For compressed instruction c.lui, the 6-bit immediate is left-shifted by 12 bits in decoding. While the original Gem5 gives the left-shifted value directly in disassembly. This patch fixes the problem by adding a new template CILuiExecute to resume the immediate before outputting it in disassembly. Note: The immediate is sign-extended to 20-bit to be compatible with GCC. Change-Id: If73f72d3e8f85a8b10ce7a323379d8ad6c4c3085 Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22567 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-28dev-arm: Automatically assign PCI device ids in attachPciDeviceCiro Santilli
Simulation scripts currently need to assign PCI device addresses when adding new devices. This change moves this responsibility to the VExpress_GEM5_BASE::attachPciDevice method. Change-Id: I6d62af8a8f9176d964cc011dd8fb9744154bbb87 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22830 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-28dev-arm: device name in AmbaFake accessesAdrian Herrera
This patch prints the name of the AmbaFake device being accessed. This is useful for identifying the device triggering the warning. Change-Id: I69ca06d5d9bce73d918b8c8b46bb43e92597933b Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22847 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-28mem-cache: Avoid hiding a virtual method in the dictionary compressor.Gabe Black
The non-virtual version is later used in overrides of the virtual version whcih takes more arguments. Change-Id: I102d1185c7a616337c2a0429daa998706189292f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23127 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-28mem-cache: Remove a std::move clang says is unnecessary.Gabe Black
It also says it prevents an optimization. Change-Id: I9c21dc1a0c53cf70cefd1400564de07d1e845a75 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23124 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-28arm: Make sure not to shift off of the end of a uint32_t in KVM.Gabe Black
The methods which set or get an attribute from the virtual GIC use a shift constant which is 32, but they store their result in a 32 bit variable and, according to clang, are used to shift 32 bit inputs. This is undefined behavior in terms of the shift, and will truncate off the value regardless. Change-Id: Ie9543ab9e6e1d5f86317a9210d220928b23ffaf8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23129 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-27base, python: Allow dirname selection for the interpreterGiacomo Travaglini
This is the second step towards being able to run dynamically linked applications when the guest ISA != than host ISA. Once the guest interpreter is loaded to memory, we are able to redirect shared object loads through the redirectPath interface. How do we load the guest interpreter? The elf file is for example asking for the /lib/ld-linux-aarch64.so interpreter. That would point to a valid dynamic linker/loader if guest ISA == host ISA, but if we are running on X86 we should point to the guest (aarch64 in the example) toolchain wherever it is installed. This patch is adding the --interp-dir option to point to the parent folder of the guest /lib in the host fs. Change-Id: Id27b97c060008d2e847776a49323d45c8809a27f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23066 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-27base: Fix DPRINTF_UNCONDITIONAL on gem5.fastGiacomo Travaglini
Change-Id: I1e559f9c5daae1e9af307cd352791c1b1ac9bbdb Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23108 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-27sim-se: Check Path redirection when mmappingGiacomo Travaglini
Every syscall file access should go through the redirection process Change-Id: I1ba2063b5a254e11f47392bdad0bf0887ba73d3d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23063 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-26sim: prefix --debug-flags Event logs with the flag nameCiro Santilli
Sample output of FmtFlag,ExecAll,Event: 0: Event: Event_70: generic event rescheduled @ 18446744073709551615 0: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue 0: Event: AtomicSimpleCPU tick.wrapped_function_event 500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+4 500: Event: AtomicSimpleCPU tick.wrapped_function_event 1000: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+8 1000: Event: AtomicSimpleCPU tick.wrapped_function_event 1500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+12 1500: Event: AtomicSimpleCPU tick.wrapped_function_event Change-Id: I7f252b57d7778a15a3dda40d909bdb4425557a40 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22009 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-26cpu: prefix ExecEnable to the native trace to match DPRINTFCiro Santilli
The trace mechanism appears to be the only debug flag that does not go through DPRINTF, presumably for performance reasons. This patch manually adds that to make things uniform with other debug flags, e.g. with FmtFlag,ExecAll,SyscallBase a sample output looks like (truncated to fit into commit message lengths): 0: ExecEnable: system.cpu : A0 T0 : @asm_main_after_prologue 500: ExecEnable: system.cpu : A0 T0 : @asm_main_after_prologue+4 1000: ExecEnable: system.cpu : A0 T0 : @asm_main_after_prologue+8 1500: ExecEnable: system.cpu : A0 T0 : @asm_main_after_prologue+12 2000: ExecEnable: system.cpu : A0 T0 : @asm_main_after_prologue+16 2500: ExecEnable: system.cpu : A0 T0 : @asm_main_after_prologue+20 3000: ExecEnable: system.cpu : A0 T0 : @asm_main_after_prologue+24 3500: ExecEnable: system.cpu : A0 T0 : @asm_main_after_prologue+28 Change-Id: Ic371ebc8b0827656f1b78fcfd3f28505a5100274 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22007 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-26base: generalize ExecTicks to all messages with FmtTicksOffCiro Santilli
If FmtTicksOff is given, ticks are disabled for all log messages. The original motivation of this is to bring the implementation of native traces closer to that of other traces to help refactoring done in future patches. One additional advantage of this is that sometimes we want to compare traces of a given program under different conditions, so the start of the ROI is different, and the different initial timestamp makes a diff useless by showing differences on every line. Change-Id: Idd6cb105d301b3b9b064996043f4ca75ddafe0af Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22006 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-26base: create DPRINTF_UNCONDITIONALCiro Santilli
This is similar to DPRINTFN, but it also prints a given flag to allow communicating to users which flag enabled a given log. This is useful for logs which are enabled with DTRACE instead of directly with DPRINTF. Change-Id: Ife2d2ea88aede1cdcb713f143340a8788a755b01 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22005 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-11-26base: add the --debug-flag to DPRINTF output with FmtFlagCiro Santilli
This makes it easier to determine which messages come from which flags when enabling multiple flags at once. This commit covers the bulk of the debug messages, which use the DPRINTF* family of macros. There however macros that use DTRACE to check for enable, those will be covered in future patches. Change-Id: I6738b18f08ccfd1e11f2874b426c1827b42e82a2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22004 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-26arch-arm: Make the Tarmac parsed registers case insensitiveGiacomo Travaglini
This will make parsing more robust, considering the tarmac format changes between AA32 and AA64. Change-Id: I0e4905d70e2e494104706a4c6c75b8169deaecf9 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22845 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-26arch-riscv: Fix immediate decoding for integer shift immediate instructionsIan Jiang
The "shamt" in integer shift immediate instructions is an unsigned immediate encoded in bits[25:20]. While the original Gem5 uses bits[31:20] as an int64_t. This patch fixes the problem by: - Adding a new parameter "imm_code" for format IOp and use the correct bitfields SHAMT5 or SHAMT6 to assign "imm_code" for each instruction. - Use uint64_t instead of default int64_t to assign parameter "imm_type" of format IOp. The instructions affected include: - Shift Left Logical Immediate, slli - Shift Right Logical Immediate, srli - Shift Right Arithmetic Immediate, srai - Shift Left Logical Word Immediate, slliw - Shift Right Logical Word Immediate, srliw - Shift Right Arithmetic Word Immediate, sraiw Change-Id: Iad34ccd036c11630409f84f6de2b939224e100e6 Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22563 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-26arch-riscv: Fix disassembling for fence and fence.iIan Jiang
The original Gem5 does not give correct disassembly for instruction fence and fence.i. This patch fixes the problem by adding two bitfields PRED and SUCC and a new format FenceOp and a template FenceExecute, in which operands are generated based on PRED and SUCC in the disassembling function. Change-Id: I78dbf125fef86ce40785c498a318ffb1569da46c Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22569 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-26arch,cpu: Get rid of ISA_HAS_CC_REGS and its associated ifdefs.Gabe Black
This conditional compilation was unnecessary and makes gem5 more brittle and harder to understand. Change-Id: I63abaf2668252c988cdd4626ff6a462eb6f54b04 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22544 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-25arm: Stop serializing ISA values wihch are cached from the system.Gabe Black
These values are not really part of the ISA state and could be retrieved from the system during execution. Also these values are already being set in the ISA constructor. Change-Id: Iea5f9bbb27add4ecebc6391da6c1c1e49e76508f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22543 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-25arch-arm: default MIDR for Armv8 ISA processorsAdrian Herrera
Software such as Trusted Firmware-A checks the MIDR register to identify which core model is present in the platform. The previous default value referred to a Cortex-A15 Armv7-A processor, however when AArch64 is enabled, an Armv8 processor is expected. This patch assigns the Cortex-A57 MIDR if AArch64 is enabled. Change-Id: Id1677a77d2f04843423f7b013405445f3d253399 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22846 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-25dev-arm: Adjust off_chip ranges in VExpress_GEM5 platformGiacomo Travaglini
This is need after commit b4c9996d894118be04cdf4ed793b35a1d5001942 which makes the AddrRange end address non inclusive. Change-Id: I859b84f6a91107815236b67c4596291c78881fe3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23003 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-25cpu: log thread activate and suspend with --debug-flags ThreadCiro Santilli
The original motivation of this is to help debug syscall emulation deadlocks. Change-Id: I1c4f611fa2f2e464a30dc92baac89ca819e16a97 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21759 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-25sim-se: don't wake up threads that are halted on futexCiro Santilli
At Ia6b4d3e6148c64721d810b8f1fffaa208a394b06 the futex wake up started skipping selecting threads that are already awake, which already prevented some deadlocks. However, threads that are Halting or Halted should not be woken up either, as those represent cores in which processes have already exited. Before this commit, this could lead an exited core to wake up, which would then immediately re-execute the exit syscall, and possibly leave one genuinely sleeping core locked and: Exiting @ tick 18446744073709551615 because simulate() limit reached Change-Id: I1531b56d605d47252dc0620bb3e755b7cf84df97 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22963 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-25arch-riscv: Fix disassembling for atomic instructionsIan Jiang
The original Gem5 does not give correct disassembly for atomic instructions, which are implemented with one or two micro instructions. The correct register indices are not decoded until subsequent micro instruction is processed. This patch fixes the problem by getting the register indices and other properties (aq and rl) from certain bitfields of the machine code in the disassembling function. Change-Id: I2cdaf0b3c48ff266f19ca707a5de48c9050b3897 Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22568 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-11-25arch-riscv: Fix disassembling of operand list for compressed instructionsIan Jiang
In disassembling compressed instructions, the original Gem5 gives needless operands, such as register or immediate. This patch fixes the problem. - Existing formats fixed: CIOp, CJOp, CBOp and Jump. - New formats added: CIAddi4spnOp (for c.addi4spn only) and CompressedROp (with templates CBasicDeclare and CBasicExecute) Change-Id: Ic293836983256a59d3a7aca091c8184b410516a4 Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22566 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2019-11-25arch-riscv: Fix disassembling of immediate for U-type instructionsIan Jiang
For U-type instructions auipc and lui, the 20-bit immediate is left-shifted by 12 bits in decoding. While the original Gem5 gives the left-shifted value directly in disassembly. This patch fixes the problem by - Assign the original 20-bit immediate to internal variable "imm". - Output "imm" directly in disassembly, as how the original Gem5 does. - Do the left-shift to "imm" later in the function defining of each instruction, rather than in decoding. Change-Id: I300e26fd9c79478783c39fcd6ff70ea06db88884 Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22564 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-11-22arch-riscv: Fix bug in serialize and unserialize of InterrutpsIanJiangICT
When serialize and unserialize an variable, the parameters passed to SERIALIZE_SCALAR() and UNSERIALIZE_SCALAR() must be the same and should be a general variable name. If not, the expected item would not be found with UNSERIALIZE_SCALAR() and a fatal error would be introduced. This patch fix the bug in class Interrupts of RISCV. Change-Id: I7dd7ab6805651149304959bdf7ee9f3be9d9eaff Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22643 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2019-11-21scons: Use the new error() and warning() methods.Gabe Black
Also clean up some error messages which were missing capitalization, etc. Change-Id: Iaef6b4343a693d30b579e72218cbb7723ebf7d48 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22886 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-21scons: Use HAVE_PROTOC when building protobuf files.Gabe Black
Also wrap PROTOC in {}s which is better form. Change-Id: I3f80c260593a1d5b7fb5394fe4b71cb774e652ce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22884 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-21tests,base: Added GTests for exec_ecoff.h and exec_aout.hBobby R. Bruce
Change-Id: Iec76ba24a06425caefd28d640c6479720f401c06 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22323 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-21test,base: Added GTest for base/loader/image_file_data.ccBobby R. Bruce
image_file_data.cc reads an image file, or an image file compressed with gzip. Mock image file data, and that data in a gzipped state, has been included in base/loader/small_image_file.test.hh to aid testing. Change-Id: I69691b93ca03c34d6bd736cbc5c6503115bd7b3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22743 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-21base: Remove tests making use of Big/LittleEndianOrder NamespaceGiacomo Travaglini
Unit tests are currently broken. commit d40f0bc579fb8b10da7181d3a144cd3e9a0a0e59 is removing the BigEndianOrder and LittleEndianOrder namespace. Therefore we shouldn't test them and their helpers. Change-Id: I68a45f264b782334d0a0f725c2c435c27337e757 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22943 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-20base,tests: Expanded GTests for addr_range.hhBrandon Potter
These tests assume the "end address" is not included in the range. This exposed some bugs in addr_range.hh which have been fixed. Where appropriate code comments in addr_range.hh have been extended to improve understanding of the class's behavior. Hard-coded AddrRange values in the project have been updated to take into account that end address is now exclusive. The python params.py interface has been updated to conform to this new standard. Change-Id: Idd1e75d5771d198c4b8142b28de0f3a6e9007a52 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22427 Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-20tests, base: Added GTests for base/intmath.ccBobby R. Bruce
Testing intmath.hh and intmath.cc. Here is the list of the functions that are tested. intmath.isPowerOf2, intmath.power, intmath.floorLog2, intmath.ceilLog2, intmath.divCeil, intmath.roundUp, intmath.roundDown. Other functions are not tested, because they are not currently used and are dead code. Change-Id: I150ac1b5cead93c6698a8c9e9cec80bd87ef181a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22081 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Mahyar Samani <msamani@ucdavis.edu> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-11-20tests, base: Removed dead code from base/intmathMahyar Samani
The below list of functions were dead code and are now deleted. intmath.prevPrime, intmath.isPrime, intmath.leastSigBit, intmath.floorPow2, intmath.ceilPow2, intmath.isHex, intmath.isOct, intmath.isDec, intmath.hex2Int. The source file intmath.cc is now effectively useless and deleted. Change-Id: I28e4350056b8d03e02fecd5c7f7f9c62bc2df7ce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22584 Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com>
2019-11-18arch: Get rid of the (Big|Little)EndianGuest namespaces.Gabe Black
These namespaces were used to set up an environment/context where there was an implicit guest namespace. This is an issue when there may be multiple guest endiannesses which might be different. In cases where we don't know what the guest endianness is, we can't rely on it being an implicit part of our context since that would be ambiguous. In cases where we do know, for instance in ISA specific code, we can just use the endianness specific version that's appropriate for that context. This also (somewhat) removes the assumption that there is a single endianness that applies for a particular ISA. Practically speaking this assumption will probably still stand though, since there would likely be a non-trivial performance penalty to apply a configurable endianness instead of a fixed one the compiler can optomize/remove. Change-Id: I2dff338b58726d724f387388efe32d9233885680 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22374 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18arch: Make and use endian specific versions of the mem helpers.Gabe Black
Rather than using TheISA to pick an endian conversion function, we can have a version defined for big and little endian and call the right one from the ISA code. Change-Id: I5014504968952e21abff3c5f6cbe58ca24233f33 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22373 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18arch-arm: R/W interface to AArch32 HCR2 misc regAdrian Herrera
This patch implements read/write interfaces to HCR2 AArch32 register, which is mapped to the upper 32 bits of HCR_EL2. Change-Id: I996023f3ad8233457d19de8a506ebcf106409165 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22832 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18mem-cache: Initialize all members of `QueuedPrefetcher::DeferredPacket`.Isaac Sánchez Barrera
Members `tc` and `ongoingTranslation` were uninitialized in the constructor for `QueuedPrefetcher::DeferredPacket`. If `ongoingTranslation` is not initialized to `false` by default, some translation requests from queued prefetchers are not properly handled and executions are nondeterministic. Change-Id: Ia278f9e74847d6b847984d47f6a45643bae57794 Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22844 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18mem-cache: Fix destructor of `BasePrefetcher::PrefetchInfo`.Isaac Sánchez Barrera
The destructor of `BasePrefetcher::PrefetchInfo` was calling `delete` for a dynamically-allocated array. Changed to `delete[]` to remove potential undefined behaviour. Change-Id: I6f531bfb6fb7108f1d3e743ae0384d80173e15ef Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22843 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18arch-arm: Fix short descriptors cacheability during table walksGiacomo Travaglini
This implies checking for the SCTLR.C bit TTBR1.IRGN0 bits. Change-Id: I341faf85692ce2d2b4afd30a2f4aabac0e133192 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22724 Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18arch-arm: Fix long descriptors cacheability during table walksGiacomo Travaglini
Prior to this patch table walks were always cacheable unless cacheability was globally disabled by SCTLR.C being 0. Arm allows to select the memory attributes of table walks via the TCR registers. For example the TCR.IRGN0 bits: Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. IRGN0 Meaning 0b00 Normal memory, Inner Non-cacheable. 0b01 Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable. 0b10 Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable. 0b11 Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable. Note: we check IRGNx bits (Inner Shareable domain) instead of ORGNx (Outer Shareable domain) since in gem5 we consider everything as Inner Shareable. Change-Id: If472c218040029c9d165b056a052f522d48d4a82 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22723 Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-16tests: Added GTests for byteswap.hhBobby R. Bruce
In addition to the test, "#include base/logging.hh" was added to the "byteswap.hh". It is is required to compile the header. Added tests ByteswapTest.swap_byte64, ByteswapTest.swap_byte32, ByteswapTest.swap_byte16, ByteswapTest.swap_byte, ByteswapTest.htog, and ByteswapTest.gtoh. The file byteswap.hh is mostly templates. Added test for BigEndianGuest and LittleEndianGuest namespaces. Change-Id: I8870a55594ed439fe9e1fb333384f73261d1b1b8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22080 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-14tests, base: Removed ambiguity from base/intmath.hhMahyar Samani
The function intmath.leastSigBit is ambiguous given its name. It does not return the value of the least significant bit, or the position of the least significant set bit, but instead 2 to the power of the position of the least significant set bit. It has thereby been removed and the function intmath.isPowerOf2 has been refactored to not require intmath.leastSigBit. Change-Id: I22479c666cdd059865b8c73b70b5388f98a4584d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22583 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-14arch-arm: Refactor code to check if gic is GicV2Chun-Chen TK Hsu
Refactor code to use cpu_addr only when gic is GicV2 since cpu_addr is only meanful to GicV2. Test: Boot Android P successfully with the following command: M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt ./configs/example/arm/fs_bigLITTLE.py --dtb $PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb --kernel $PWD/fs_files/binaries/vmlinux --disk $PWD/fs_files/disks/disk.img --kernel-init "/init" --cpu-type fastmodel --machine-type VExpressFastmodel --big-cpu-clock "2GHz" --big-cpus 1 --little-cpus 0 --mem-size 8GB --kernel-cmd "earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=8GB root=/dev/vda1 init=/init androidboot.hardware=gem5 qemu=1 qemu.gles=2 android.bootanim=0 vmalloc=640MB android.early.fstab=/fstab.gem5 androidboot.selinux=permissive audit=0 cma=128M" Change-Id: Iedd1388f292685c25f1effcd2e14b3db8899dff9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21339 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-14config: Add fastmodel cluster in fs_bigLITTLE.pyChun-Chen TK Hsu
One can create a system with ARM FastModels CPU and GICv3 with --cpu-type fastmodel --machine-type VExpressFastmodel options. Currently the FastmodelCluster only supports one CPU. Change-Id: I2e985f08f9df01a703e21441c6f9bc1fbae4a222 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20901 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-14fastmodel: Add VExpressFastmodel platformChun-Chen TK Hsu
A VExpress based platform with FastModelGIC as interrupt controller. Change-Id: I5ef6d04573d271225d7b39c110e93350a290c371 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21359 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-13arm: Replace most htog and gtoh with htole and letoh.Gabe Black
We already know what endianness to use when with ARM. In places where a ISA was being supplied through an argument, those were left as htog or gtoh. Change-Id: Iff01e8b09a061d9a72e657cdd4570836e0da933f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22372 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-13arch-arm: fix routeToHyp for AArch64 in faultsAdrian Herrera
This patch fixes several bugs in Fault classes "routeToHyp" member function by which mode checking was not taking into account AArch64 execution state. For the particular case of SVC calls from NS EL0, this prevented a correct routing to EL2 when HCR_EL2.TGE was set. Change-Id: I5815fe6dcf4501f52bf92f61687ef6d6ef950e52 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22725 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-20 04:41:14 +0000