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2019-11-13tests: Added GTests for base/chunk_generator.hhBobby R. Bruce
Change-Id: Ic6ededfc7fed1f91a75e48a0933e61b4670e5af1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21679 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-13fastmodel: Implement reading vector registers with readVecReg.Gabe Black
The n other flavors of vector reading functions and all the vector writing functions are not implemented currently. Change-Id: I0c25c3ba47c7e4072da3d28596f44f6073b6f609 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22117 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-13tests: Added GTests for base/types.ccBobby R. Bruce
Change-Id: I9515735efdd452a9f8c98f37f4ec2c27120929f5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21659 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-12tests,base: Added GTests for base/condcodes.hhBobby R. Bruce
The documentation for the "findParity" and "findCarry" functions in base/condcodes.hh has been enhanced to better explain their behavior. Change-Id: I9ba3bf68eb56529a3030e965ec21e41d2dacfad6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21639 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-11arch-arm: Fix TarmacParser handling of 64bit LD/STGiacomo Travaglini
The TarmacParser was assuming 32 bit accesses only. This was creating a mismatch when parsing a trace with 64 bit accesses. E.g. In clk IT (18) 002001f4 f8008441 O EL3h_s : STR x1,[x2],#8 clk MW8 00201008:000000201008 00000000_40000401 Only the 32 MSBs were checked (00000000) Change-Id: I51e803b53efe953edcd9378f6c9481c04932331e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21562 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-11arch-arm: Provide SVE support to the TarmacTracerGiacomo Travaglini
Change-Id: I86ff5f49a0c0aa126d53076964f208716e70aacb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21561 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-11arch-arm: Provide SVE support to the TarmacParserGiacomo Gabrielli
This patch is providing SVE support to the tarmac parser, so that it is recognizing Vector & Predicate entries. Change-Id: I268e621cffa05644d3f1d80170b067aacaa2d5ea Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21560 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07arm: Set the number of FloatRegs to zero.Gabe Black
ARM no longer uses the floating point register file and uses the vector registers instead. This avoids checkpointing a bunch of unused registers, making it hard to tell where floating point instructions are keeping their values, etc. Change-Id: I23145ba750f1dd9ff5b815395e073c410120840d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22524 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07tests,base: Added GTests for base/match.ccBobby R. Bruce
In order to aid testing the method "match.getExpressions()" has been added. Change-Id: I11acf9bed286ee2809dfa3d05ef573dea85eb786 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22503 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07cpu: Fix a bug in getCurrentInstCount in the checker CPU.Gabe Black
An earlier change accidentally left out the actualTC-> prefix in the getCurrentInstCount method which was supposed to delegate the call to another thread context. Without that, it just called itself and would infinitely recurse. This bug was pointed out in email by Robert Henry. Change-Id: Ibf1fee6b48ff87790309c6d435bd76fa95c6cab9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22623 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07power: Replace gtoh and htog with betoh and htobe.Gabe Black
We already know what endianness to use when within power. Change-Id: Id4ced279d21c56855307a5a8da51654101a13786 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22371 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07x86: Replace htog and gtoh with htole and letoh.Gabe Black
We already know what endianness to use from within x86. Change-Id: Ie92568efe8b23fbb7d9edad55fef09c6302cbe62 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22370 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07mips: Replace gtoh and htog with letoh and htole.Gabe Black
We already know what endianness to use from within MIPS. Change-Id: Ic4cd295a7a66c4c8ef55ebcf976fe6637567391f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22369 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07sparc: Replace htog and gtoh with htobe and betoh.Gabe Black
We know what endianness to use when we're implicitly working with SPARC. Change-Id: I85eaac1da087a8086b9450b762a52323f2498e2e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22368 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07systemc: Remove boost dependency caused by tlmHoa Nguyen
This commit replaces the tlm header file, which caused the boost dependency. Change-Id: Ie4b1af71202522d8139e9a861144863097188072 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22624 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07fastmodel: Plumb the ITB and DTB through the IRIS thread context.Gabe Black
These might be necessary to, for instance, translate virtual addresses. A custom TLB which uses the IRIS API will be written which can be substituted in for the normal ARM TLB. Change-Id: Ic44822db6692ca3a4ca13875b2260b08547a24da Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22116 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-06fastmodel: Implement inst count events in the IRIS thread contexts.Gabe Black
These use the IRIS stepping API. Change-Id: Ib45744cb0928fece664187e4df6b25b064b19f0e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22115 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-06arch-arm: Simplify AMO code generation templatesNikos Nikoleris
This change simplifies the isa template for the atomic memory operation (AMO). Previously the flow had unecessary if statements that ended up breaking build using clang, due to variables that could seemingly be used before they were unitialized. Change-Id: I1b46dfd5f1e90377245c4f649c08b6532b507b9c Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22603 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-06cpu: Use std::array for registers in SimpleThread.Gabe Black
If the number of one of the register types is zero (useful on ARM in the near future), memset will complain that it's given the length of the array without multiplying by the size of the array elements. This is a false positive since the length of the array and the number of elements are both zero. To avoid that warning/error and to simplify and update the SimpleThread class slightly, this change replaces the C style arrays with std::array. Change-Id: Ifedd081a1940a578765c4d585e623236008ace67 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22523 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-05arch-arm: Annotate original address in CMOsGiacomo Travaglini
This is needed when a CMO triggers an exception (e.g. DataAbort) In that case the faulting address should be the one encoded in the instruction rather than the cacheline address: According to armarm: If a memory fault that sets FAR_EL1 is generated from a data cache maintenance or other DC instruction, FAR_EL1[63:0] holds the address specified in the register argument of the instruction. Change-Id: I6d0dadbef6e70db57438b01a76c5def3bdd2d974 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22443 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-05mem-ruby: Reset Ruby Sequencer Outstanding Requests statsPolydoros Petrakis
Change-Id: I14b106e0eb7abd9c14badeedf35d6d1c9f198f98 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22446 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-05dev-arm: optional instantiation of GICv3 ITSAdrian Herrera
GICv3 ITS is an optional component of GICv3. The previous behaviour was for a stub ITS to be created by default, which resulted in a crash for use cases where a GICv3 with no ITS is required. This patch removes the instantiation of the ITS by default and adds checks for its presence both in initialization and device tree generation code. Change-Id: Id424924c8c1152d512aaa2837de4aa60329ec234 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22423 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-04mem-cache: Modify compressor to appease newer compilersDaniel R. Carvalho
The type of the local unique_ptr variable was different from the return type. In C++11 because of such difference, a copy-ellision would not be possible, and that required the use of a std::move. In C++14 the restriction of same types being required was removed, so std::move would not be needed anymore. With the addition of the -Wredundant-move warning in newer compilers, having the std::move on the return became an issue, breaking compilation. Change-Id: I45d18dfc500bb5db5fe360814feb91853c735a19 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22403 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-11-04mem-cache: Implement a perfect compressorDaniel R. Carvalho
Implement a perfect compressor that always manages to compresses data exactly to its maximum allowed compression ratio. This allows tracking a compression upper bound. Change-Id: Ibc68bf2dc84b75207795d5ba6304b9ed6dbeae8f Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21160 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Make BDI a multi compressorDaniel R. Carvalho
BDI is a compressor containing multiple sub-compressors. Change-Id: I98411e2ef9dcc2182801a172dfc59ed7a8ee7dd4 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21159 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement a multi compressorDaniel R. Carvalho
Implement a compressor that contains multiple sub-compressors and choses the one that provides the best compression results for each compression. Change-Id: I758cf67c84bd85edbea16b2a07b2068b00454461 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21158 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-04mem-cache: Implement BDI sub-compressorsDaniel R. Carvalho
Implement sub-compressors of BDI as public compressors so that they can be used separately. Change-Id: I710e35f39f4abb82fd02fd33b1b86a3f214c12cb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21157 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement a repeated values compressorDaniel R. Carvalho
The repeated values compressor can only compress data composed solely repeated instances of the same value. Change-Id: If2c4f47ad4af492d202ec2017e30ba52ee67e307 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21156 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement a zero compressorDaniel R. Carvalho
The zero compressor can only compress data composed solely of zero bits. Change-Id: I8b359c03776a8748abd144a178bda944b5a1b766 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21155 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement FPC-D cache compressionDaniel R. Carvalho
Implementation of Frequent Pattern Compression with limited Dictionary support (FPC-D) cache compressor, as described in "Opportunistic Compression for Direct-Mapped DRAM Caches", by Alameldeen et al. Change-Id: I26cc1646f95400b6a006f89754f6b2952f5b4aeb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21154 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-02arch,cpu: Move endianness conversion of inst bytes into the ISA.Gabe Black
It doesn't matter if the bytes are converted before or after they're fed into the decoder. The ISA already knows what endianness to use implicitly, and this frees the CPU which doesn't from having to worry about it. Change-Id: Id6574ee81bbf4f032c1d7b2901a664f2bd014fbc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22343 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-01mem: Delete the packet accessors which use guest endianness.Gabe Black
These accessors create an extra dependency on the guest OS, and can be avoided. Now that all their uses have been removed, they aren't needed any more. Change-Id: I466c07fef99bce2d7964c07a7ac3dd398691378b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13465 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-11-01arch-x86: Fix FLDCW_P and FNSTCW_P to use rip.seanzw
FLDCW_P and FNSTCW_P should use rip to compute address. Change-Id: Ide7327e243d42bdd8791e43773385b2a79d45418 Signed-off-by: Zhengrong Wang <seanzw@ucla.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22483 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-01arch-arm: generic method for getting an ArmSystemAdrian Herrera
This patch provides a generic method for casting a System object into an ArmSystem object. This is specially useful in dev-arm, since devices by default obtain a generic System reference which needs to be casted to use ArmSystem-specific functionality. Change-Id: Ib100002413cb48cd93772dcf38f13be65badd1d3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22426 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-01dev-arm: Add SMMUv3 to VExpress_GEM5_V*Giacomo Travaglini
The VExpress_GEM5_V* Platforms will now optionally make use of the SMMUv3. In order to attach a devices to it, a user must simply use the attachSmmu method, making sure the device it is not part of the _on_chip_devices(). Change-Id: Ib819eb50d43dba1f5e5d1a1f7159ac4fbaccff6e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21559 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31fastmodel: Add CortexA76x[234] models.Gabe Black
These use the parameterization added in earlier commits. Change-Id: Id7b99b97894f8fc1f1e5cc34e3e5d32146fed1c7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21505 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31fastmodel: Enable auto bridging and use it to simplify CortexA76x1.Gabe Black
This lets us avoid having to set up bridges for all the different interrupt signals coming out of the CPU. When we have more cores, like in the x2, x3, and x4 versions of the CPU, we won't have to have a set of bridges for each set of signals, and can connect them all to external ports using array notation, keeping everything simple, concise, and maintainable. Change-Id: I1a5f707073868516e93c106dc17d105409de668a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21504 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31fastmodel: Templatize the xn versions of the CortexA76.Gabe Black
This will make it a lot easier and more succinct to define the x2-x4 versions of that CPU. Change-Id: I951cd3af4419c62892c57968e729fd11c0e4a59e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21503 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31mem-cache: Fix missing header in associative setDaniel R. Carvalho
Add missing intmath header to AssociativeSet, so that isPowerOf2 can be used. error: there are no arguments to 'isPowerOf2' that depend on a template parameter, so a declaration of 'isPowerOf2' must be available Change-Id: Ib2b194f9e71284ee439786bdb76d99858e57e2f5 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22444 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31mem-ruby: Fixed pipeline squashes caused by aliased requestsJoe Gross
This patch was created by Bihn Pham during his internship at AMD. This patch fixes a very significant performance bug when using the O3 CPU model and Ruby. The issue was Ruby returned false when it received a request to the same address that already has an outstanding request or when the memory is blocked. As a result, O3 unnecessary squashed the pipeline and re-executed instructions. This fix merges readRequestTable and writeRequestTable in Sequencer into a single request table that keeps track of all requests and allows multiple outstanding requests to the same address. This prevents O3 from squashing the pipeline. Change-Id: If934d57b4736861e342de0ab18be4feec464273d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21219 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31cpu-o3: bugfix for partial faults in x86Brandon Potter
The c58cb8c9 changeset broke some code related to checking consistency model guarantees (found in X86 benchmarks). This changeset adds some documentation to the code and obviates the problem. Change-Id: Ied9c6b0b1d237538efe4beb2f97ef76248ce2746 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22283 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2019-10-31alpha: Convert htog and gtoh to htole and letoh.Gabe Black
When within the Alpha arch, we know the guest endianness already. Change-Id: Iee22a33451a06c6e6a5c7d1e8c71f0b00e98ae3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22367 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-10-30arch,sim: Make copyStringArray take an explicit endianness.Gabe Black
Change-Id: I5cf4291b19dd2d2bdbbf145ad8e00994fabf5547 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22366 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30kern: When dumping dmesg, detect the byte order dynamically.Gabe Black
The dmesg dumper has access to the system object and so has access to the getGuestByteOrder accessor. Use that instead of TheISA to determine the byte order. Change-Id: I4df7b1bcd807aaced1d7dc8d2030123e2d4d1d2b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22365 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30sim: Use the system and OS to get endianness.Gabe Black
This converts the syscall implementations to either use the OS::byteOrder constant or, if that's not available, the system's getGuestByteOrder() accessor, to determine the byte order, instead of relying on TheISA to provide the correct accessor. Change-Id: Idf7b02ee8d73990224ceac9a5efaec91a5ebf79f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22364 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30arch: Make endianness a property of the OS class syscalls can consume.Gabe Black
That way the syscall implementations won't have to find the right endianness to use on their own, typically by referring to TheISA. Change-Id: I186b2f419d5dbee72cc9b5abce7356f3143f0c83 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22363 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30dev: Make the virtio devices track endianness explicitly.Gabe Black
These classes now track what endianness they're supposed to use explicitly, initially set by the getGuestByteOrder accessor on the system object. In the future, if the endianness depends on the version of the VirtIO spec as the comment suggest, it will be easier to dynamically set the endianness in the various structures based on the version being used, Since there isn't anything special about the virt IO versions of these converters other than their types, and since the endianness conversion infrastructure can be taught how to convert new types, the code was switched over to using the standard htog and gtoh but with the explicit byte order provided. This also gets rid of the final use of TheISA in the dev directory. Change-Id: I9345e3295eb27fc5eb87e8ce0d8d424ad1e75d2d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22273 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30sim: Add a getGuestByteOrder accessor to the system class.Gabe Black
This goes along with the existing getPageBytes, etc., accessors, and paves the way for this to be a parameter of the System class. Change-Id: Ibfe2d591185d23beccdd5bbff1092dc07b1278ac Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22272 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30fastmodel: Refactor the CortexA76x1 model for MP support.Gabe Black
This change inverts the relationship between the fast model and gem5 CPUs, and factors out the parts of the CortexA76x1 which are per core vs. per cluster. Change-Id: I33eacc2461f08c7fd1784936b230e96c768c0e79 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21501 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30dev: Adding support for large BARPouya Fotouhi
During PCI setup, this patch checks if a Base Address Register (BAR) is used as a large BAR (64 bits rather than 32), and return proper address range. The order which updates are done is decided by kernel, so this patch implements both cases (writing lower or upper bits first). Bit 2 in a BAR indicates a 64-bit decoder (10X to be more exact, 11X is reserved). The addresses in BARAddrs are full addresses and are set to zero for BAR providing upper 32 bits to avoid conflicts in addr ranges reported. Change-Id: I93303d36ac83dab9ed6837c81e77c9dfb778f409 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22082 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-20 05:58:16 +0000