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2019-09-19arch-arm: PSTATE.PAN changes should inval cached regs in TLBGiacomo Travaglini
Change-Id: Id94e355fec345d2e952539a7dce7fbd21ed220c6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20983 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-18arch-arm: Fix Data Abort ISS when caused by Atomic operationGiacomo Travaglini
Data Aborts caused by an atomic instruction have a special rule for their syndrome: From a ISS point of view they count as read if a read to that address would generate a fault; they count as writes otherwise (ISS.WnR bit) This patch is implementing this in the TLB. For permission faults we need to explicitly check if a read would trigger a fault (e.g. checking for the AP bits) since permissions can allow read-only accesses. For other MMU exceptions (like translation faults) we are confident the nature of the access doesn't affect the genration of a fault. This means that if the access is atomic, we treat it as a read from an ISS.WnR point of view. Change-Id: Ia524aa6ae07f81513cdc26c516b5fd9b01a931c3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20981 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-18arch-arm: ISV bit in DataAbort should check for translation stageGiacomo Travaglini
According to the ESR spec, the ISV bit is set to 1 only for stage 2 aborts. Change-Id: Id524ef36e82184f741e968ddba04ca8ccdd4ad58 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20980 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-18arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2.E2H=1Giacomo Travaglini
Change-Id: I6df0cdcbadca17f30d3de3bed887f75c739b00f0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20979 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-18arch, x86: Rework the debug faults and microops.Gabe Black
This makes the non-fatal microops advance the PC, and adds missing functions. The *_once Faults now also can be run once per *something*. They would previously be run once per Fault invoke function which is common to all M5WarnOnceFaults. The warn_once microop will now warn once per message. Change-Id: I05974b93f3b2700077a411b243679c2ff0e8c2cb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20739 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-17systemc: Make TLM port wrappers for tlm_base_(target|initiator)_socket.Gabe Black
These are useful if using TLM sockets without using the standard TLM protocol. For instance, when used with ARM's fast models, this can wrap sockets which carry the opaque GICv3Comms protocol. Change-Id: I329a919068f958abbde2cb83683d3a3ae2e05a20 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20860 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-17systemc: Expose the utility functions for payload->packet conversion.Gabe Black
These can be used anywhere someone needs to turn a packet into a payload or vice-versa. Change-Id: I26a1f134e6fbec81b230a2853cf79264e80bf2dc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20859 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-16dev-arm: Allow IOMMU binding to HDLcdGiacomo Travaglini
Change-Id: I894080e7bd76e7efedef141c937e1561c0c0527c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20841 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-13dev-arm: Store the IOMMU reference from within the SMMU::connectGiacomo Travaglini
Change-Id: I35718a71dc040ee4acad9eee2a07076ebb571304 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20840 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-13dev: Enable DTB IOMMU binding with a DMA objectGiacomo Travaglini
This happens by storing a iommu reference in the dma device, and by calling the addIommuProperty method once doing dtb autogeneration for the device Change-Id: Ibd585addac686a9eeaba6959f459d81901087549 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20839 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-13sparc: Fix a warning/error in tlb.cc.Gabe Black
gcc has started to not like memseting an ojbect to zero in some cases. Cast the TlbEntry pointer to a void * before memsetting it to placate gcc. Change-Id: Iccb3c326fdb82f1f111329ff1a80bb6719cace47 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20830 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-09-12dev: Generalize the x86 int source/sink pins.Gabe Black
Sink pins are now templated based on the underlying device types, and the pins themselves are based on the new, generalized Port mechanism. Change-Id: I09c678c56f6eb6b4a167c12f221ae0241fe99c2d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20700 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-12mem-cache: Fix BDI size calculationDaniel R. Carvalho
The bitmask field indicates to which base a delta refers, and in the original paper it is fixed and proportional to the highest number of bases allowed in the compressed data. Change-Id: I271bf2e19e0765de52b933eaf6d4fcc2ce25d185 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19748 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-12base: Add a perfect bloom filterDaniel R. Carvalho
Add a bloom filter that keeps track of all observed entries, and thus has no false negatives nor false positives. Change-Id: Iba784e617a99c77554c688470d9b9e12c260f23b Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18879 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-09-10stats: Add M5_VAR_USED to variableTommaso Marinelli
Fixes compile error for gem5.fast due to unused variable. Change-Id: Ib1664b100e95a741174610f8cdbdebaff9635f66 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20759 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-10stats: Fix incorrect name conflict panic with grouped statsAndreas Sandberg
Info::setName() performs a sanity check to ensure that the same stat name isn't used twice. This doesn't work for new-style stats with a parent group since the name is only unique within the group. Disable the check for new-style stats since these usually use names generated from member variable names. Change-Id: I590abe6040407c6a4fe582c0782a418165ff5588 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20760 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-10stats: Ignore non-Group objects in stat hierarchyChun-Chen TK Hsu
Some objects, such as SystemC modules, are not a subclass of Stat::Group. Calling the addStatGroup function on them causes errors. This changes ignores those objects that are not Stat::Group in the stat hierarchy. Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Change-Id: I9b62419417b7af7331461fbfaf15e45a4ee2b35f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20680 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-10base: Make Bloom Filter counting by defaultDaniel R. Carvalho
Since a boolean bool filter is a saturating bloom filter with a single bit per entry, generalize them by using SatCounter instead of int for the filter entries. Change-Id: I7f54e28d54de5671e0770b02ed9161735e6bd339 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18877 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-09-10base: Make Bulk inherit from MultiBitSel Bloom FilterDaniel R. Carvalho
Cleanup bulk's code and make it inherit from MultiBitSel. Change-Id: I83154feb30bb3dac3d02743bcafbdcb57489c2fd Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18876 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-09-10mem-ruby: Move Bloom Filters to baseDaniel R. Carvalho
All Bloom Filters are completely independent of Ruby, and therefore can be used everywhere. As a side effect, Ruby was not using the filters, so their dependency was removed. Change-Id: Ic5f430610c33c0791fb81c79101ebe737189497e Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18875 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-09-10mem: Mark MemObject as deprecated.Gabe Black
It's constructor will now warn that it's deprecated and suggest using ClockedObject directly. This change also gets rid of the params() method and the Params typedef since they are functionally equivalent to the ClockedObject versions. It also removes the include of mem/port.hh which is not used in mem_object.hh. This may break code which purposefully or (more likely) accidentally depended on that transitive include from mem_object.hh. Change-Id: I6dab3ba626e3f3ab6a6bd86edcf4f5cb4d6d2c45 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20720 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-09dev-arm: Reset HPPI when clearing an LPIGiacomo Travaglini
Change-Id: I2a69e6cef69aa48d7c265d59915b859e5eac2bcc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20638 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Add resetHppi method in the GICv3 cpu interfaceGiacomo Travaglini
The method is used for resetting the highest priority pending interrupt interrupt from the cpu interface if it matches the intid passed as an argument. Change-Id: I9fbc4cb3e05a1cc32f853b6afab5c2bc99369435 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20637 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Cleanup GICv3 initializationGiacomo Travaglini
This patch is removing the unnecessary initState() / reset() methods from GICv3 classes, since we can initialize everything at construction/init time Change-Id: Ia70edcc4ca4f11878fac0024342e4f2cd81883a0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20636 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Initialize GICD_TYPER once at construction timeGiacomo Travaglini
Change-Id: Ib4dfdf7005709c22b4ba95099b1192f6edd6ff06 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20635 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Writes to IGRPEN1_EL3 triggering updateGiacomo Travaglini
Change-Id: I56804eb1bfc8913bd0d3cab05865a382bf270bc1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20634 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Fix GICv3 ITS cmdq wrappingGiacomo Travaglini
Change-Id: I979e8d1378d5b5d2647158798479cf4238f2c349 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20633 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Fix mapping between IGRPEN1_EL3 and IGRPEN1_EL1Giacomo Travaglini
Previous mapping was wrong because it was checking which security bits it was accessing by using the inSecureState() function, whereas it should have used the isSecureBelowEL3(). This patch is not making the sostitution since it is optimizing the mapping furthermore by avoiding updating both IGRPEN1_EL1 and IGRPEN1_EL3 on writes. The IGRPEN1_EL1 register is used as a storage, and any reads/writes to IGRPEN1_EL3 is routed to that register. Change-Id: Id318ec44e19d4f844e4e3410d74d0c4f89810811 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20632 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Implement message-based SPIsGiacomo Travaglini
Change-Id: I35e79dfd572c3e0d9cadc8e0aab01befd6004ece Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20631 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev: Scrub out some lingering uses of MemObject.Gabe Black
MemObject doesn't do anything any more, and is basically just an alias for ClockedObject. Change-Id: Ic0e1658609e4e1d7f4b829fbc421f222e4869dee Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20719 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-07dev-arm: Add GICD_SGIR registerGiacomo Travaglini
The Distributor Software Generated Interrupt Register is implemented only if affinity routing is disabled. Since this configuration is currently not supported in gem5, it has to be treated as RES0. Change-Id: I9ffcb31b26fc17547f74a4f1d43ce72c59786fa8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20630 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-07python: Make the dot writer handle unconnected Port vector elements.Gabe Black
Change-Id: I5234013716cdcce5fc39e239dc3d92cd1f2b7799 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20699 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev: Enable Terminal output's dump to stdoutGiacomo Travaglini
While the default option is to dump the Terminal content in a file (e.g. m5out/system.terminal), with this patch it will be possible to choose to dump it to standard output. Change-Id: If51c2fd671fa3eb0867a855b5f7d3b0df9cad025 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20639 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-06dev-arm: State update when setting MISCREG_ICC_IGRPENx registerGiacomo Travaglini
This is because by enabling ainterrupt group at the cpu interface, we need to check if a previously pending interrupt needs to be forwarded to the PE. We are doing the same when globally enabling irqs in the distributor (GICD_CTLR). Change-Id: I80aeb87b2a58a108de899006d5a2f12eadbe6c2e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20629 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ic08ac1e7f3ebef408a83aa068ce15e9dfe2aa3cd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20628 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ide93464f62288fbe8f409f718487a15512c01295 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20627 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ib1691f1cba08251a36ceb959849b61c33cc3e93b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20626 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ib30c7a49490f05f88ddfd7572dd360cb92647f81 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20625 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Add read/writeBanked helpers to GICv3Giacomo Travaglini
These will be used by AA64 security banked registers in GICv3. Change-Id: Ia980c4f5c14187ab9c18da1d1d596562644111ae Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20624 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: Add explicit AArch64 MiscReg bankingGiacomo Travaglini
Change-Id: I89836d14491a51b1573f45c8012e3ad12b107d24 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20623 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: Use same template across all MSR instGiacomo Travaglini
Change-Id: Ifb9f1db288e401761b71ccf426e370c475e5663f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20622 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: SySDC64 Instructions (CMO) using MiscRegIndexGiacomo Travaglini
Change-Id: Ia66d6abf965b1d33579e8fa048608d99c93ff2ce Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20621 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-06dev: Fix segmentation fault in VirtIOBlockChun-Chen TK Hsu
GEM5 got a segmentation fault when the size is large in VirtIOBlock::write. This change uses a vector to avoid this segmentation fault. Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Change-Id: I26272686a6e7e39cdf2389657ecd38ce90261144 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20679 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: fix GDB stub after SVECiro Santilli
The SVE patches made registers longer by increasing NumVecElemPerVecReg, but the GDB XML was not updated to account for that, and as a result GDB connections were failing with: Remote 'g' packet reply is too long This commit introduces NumVecElemPerSimdVecReg which counts only the SIMD register sizes to get it back working. SVE GDB support is not added here. Change-Id: I4191b9f1999ae02b0308863db4cc9b5b16a27d6d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20468 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Rewrite ICC_BPR0/ICC_BPR1 handlingGiacomo Travaglini
The patch is fixing BPR reads in AA32, by removing the line Gicv3::GroupId group = misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S; Where a read to ICC_BPR0 will return a G1S group. The patch is also fixing Security banking accesses. Change-Id: I28f1d1244c44d4b8b202d3141f8380943c7c1c86 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20620 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Add GICv3 unimplemented Hyp Active Priorities Group regsGiacomo Travaglini
ICH_APxR1, ICH_APxR2, ICH_APxR3 are implemented only if supporting more than 6 bits of priority. Since this is not the case, they are currently unimplemented. According to spec, unimplemented registers are RAZ/WI. Change-Id: Ifd7f7a3d42b4575c2f7aff3b95d5a47ac1e61842 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20619 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Allow 32-bit access to GITS_TYPERGiacomo Travaglini
Change-Id: I9d19174b38ba70f82050102f955ccc162965d1fb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20618 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Cpu interface groupEnabled check for global enableGiacomo Travaglini
Gicv3CPUInterface::groupEnabled should check for global enable flags at distributor level: - Gicv3Distributor.EnableGrp0 - Gicv3Distributor.EnableGrp1S - Gicv3Distributor.EnableGrp1NS Change-Id: I1c855b0e4c2bc8f1cd0a8f086b9450f516177b08 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20617 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Check if INTID group is enabled when reading HPPIRxGiacomo Travaglini
If it is not enabled, it should return INTID_SPOURIOUS Change-Id: I4dfa8b9fcea874b4d281cd154dd38752b05e1d59 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20616 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Writing GICD_CTLR should trigger an updateGiacomo Travaglini
This is the case where an interrupt is pending, but the distributor is masking it. As soon as the group gets enabled, the interrupt should be forwarded to the PE. Change-Id: Ie428780bde7e4726688adf78dfcc4d43d1b45261 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20615 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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