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2019-08-22dev-arm: Allow 32 bit accesses to GITS_C(WRITER/READR/BASER)Giacomo Travaglini
For those registers (GITS_CWRITER, GITS_READR and GITS_CBASER) Bits [63:32] and bits [31:0] are accessible separately. Change-Id: Ibf60b5e4fd20efb21a63570e6012862e37946877 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20256 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-22dev-arm,system-arm: missing GICv3 ranges propertyAdrian Herrera
This patch adds the device tree "ranges" property to GICv3 for the VExpress_GEM5_V2 platform. It is also included in the GICv3 DTB auto generation. This allows the GICv3 ITS to be specified in the device tree. Change-Id: I00e1bb0fd45521e34820c0a23ddf047afec7aa4c Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20255 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-21arch-riscv: Update register fileYifei Liu
This patch adds mcounteren, scounteren according to Risc-V Privileged Architectures V1.10. Change-Id: I6e138a50710bc0a1e9d9c38a11fc7fcc09ed500e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20128 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-21arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0Ciro Santilli
In src/cpu/reg_class.hh, numPinnedWrites was unset because the constructors were not well factored out. Change-Id: Ib2fc8d34a1adf5c48826d257a31dd24dfa64a08a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20048 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-21base: assert that stats bucket size is greater than 0Ciro Santilli
Change-Id: I9a2264e9ee74acea1f09f01ea8f5004567ba1ea8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20049 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-21arch-arm: Fix implicit fallthrough build errorsChun-Chen TK Hsu
1942b21713 introduced implicit-fallthrough errors when compiled with GCC 8. This change adds M5_UNREACHABLE in the default case. Change-Id: I220f2b3fe39b5c3a65c0dd390915bffeafb28962 Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20268 Reviewed-by: Jordi Vaquero <jordi.vaquero@metempsy.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20dev-arm: Add redistributor-stride property to GICv3Giacomo Travaglini
This is needed since by default the model is assuming a GICv4 memory layout. Change-Id: Ic64e6a488cc1a43a56ce28f6d11b8868df102aa0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20248 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currELGiacomo Travaglini
Change-Id: I739a9be03ea5caa63540c62fd110eee86a058c4c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20252 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20arch-arm: Replace direct use cpsr.el with currEL helperGiacomo Travaglini
The patch is replacing it in places where the current EL could be using AArch32, hence leading to an incorrect ExceptionLevel. Change-Id: I99b75af2668f2c38fd88bec62e985ab7dbea80dc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20251 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20arch-arm: Overload currEL helper with CPSR argumentGiacomo Travaglini
Change-Id: I1edabc61637ecb9d30bca34b5dbcf1de12b35fe0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20250 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20arch-arm: Rewrite the currEL helper method to use opModeToELGiacomo Travaglini
Direct use of cpsr.el should be discouraged: it should be used when in AArch64 only; when in AArch32 it won't return the matching EL. Eg: when in Supervisor Mode (EL1), CPSR.M<3,0> (mode) is 0b0011, and cpsr.el will return 0 (EL0) Change-Id: I5504bd1f59980f79b2607cce435ea09245de12e5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20249 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20dev-arm: Add GITS_PIDR2 register to the ITS memory mapGiacomo Travaglini
The GITS Peripheral Identification Register #2 bits assignments are the same as those for GICD_PIDR2. Change-Id: I235008a383e08dd557d899cb3aa18202ef943f8b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20254 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20dev-arm: Add Gicv3Distributor members for GICv3 GICD_PIDRxGiacomo Travaglini
There is no need of calculating the value every time the registers are read. Change-Id: I58b87abb585fb9928959992927f00d9c000a4c35 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20253 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-19mem-ruby, arch-hsail: Removed hit latency from VIPERCoalescerPablo Prieto
Removed the dcache hit latency from VIPERCoalescer so HSAIL_X86 compiles after commit 496d5ed3e1f7dad42b0c2ebe0050d84621be8f99 Change-Id: I050a58d90f0f6356824c3c3bcb3f0b3c76d145e0 Signed-off-by: Pablo Prieto <pablo.prieto@unican.es> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19148 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-16x86: Stop CPUID from claiming we support xsave.Gabe Black
xsave is a fairly complex feature which we don't support in gem5, but we do report that we support it through CPUID. It looks like I confused it with FXSAVE which is an instruction related to SSE. This change turns that bit back off again. Change-Id: I00fc79168c5f7095b5241e870a4c8782e4385425 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20169 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-15x86: Make unsuccessful CPUID instructions zero the result.Gabe Black
The previous implementation left the registers unmodified which is technically correct since there is no defined behavior in that case or a fault to raise. That would make what happened when the following code consumed the result unpredictable because it would depend on what junk values were left in the registers. This was originally not a problem since the space of supported functions were tightly packed, but someone added a new function with a gap without adjusting this behavior. This change makes CPUID zero out RAX, RBX, RCX, and RDX when it fails. That should be more predictable and cause less flakey failures. Change-Id: If6ffb17c2969d34aff1600c0ffc32333d0b9be44 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20168 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-13sim: Add a hook Clocked objects can implement for frequency changes.Gabe Black
This hook will let them implement whatever additional behavior is necessary for when the clock changes. An alternative design for this might have made the "update" function virtual, and required anyone overriding it to call into the base class. I think that would be an inferior design for two reasons. First, the subclass author might forget to call update. Second, while it might *seem* like this would have some performance benefit since you wouldn't call into the virtual function and then call update, incurring the function call overhead twice, you're going to call into update once regardless, and then you're either going to call the virtual funciton which does nothing (the norm) or does something. In either case you call the same functions the same number of times. There may be a slight penalty in code size since the call to update may be inlined in the call sights before the virtual function, and there will almost certainly be more of those than there would be implementations of the virtual function, but that should be negligable when compared to gem5's size as a whole. Change-Id: Id25a5359f2b1f7e42c6d1dcbc70a37d3ce092d38 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20089 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-08-13sim: Clean up some mild style bugs in clocked_object.hh.Gabe Black
Clean up some formatting, and also remove redundant inline keywords. A function defined in place in a class definition is already automatically inline. Change-Id: Iaad3a8dda6498c6a6068c2aabc9d6eb11f3d2eb2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20088 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-13mem-ruby: Use check_on_cache_probe on MIPouya Fotouhi
This change uses check_on_cache_probe statement to check if the cacheline subject to eviction is locked in MI. Change-Id: I276822e987e52f7682ff30f55880f295b6af023d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19888 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-08-13mem-ruby: Use check_on_cache_probe on MOESI hammerPouya Fotouhi
This change uses check_on_cache_probe statement to check if the cacheline subject to eviction is locked in MOESI hammer. Change-Id: I2c43f22aba5af3a57e54b1c435e5d3fbba86d1d5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19891 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-08-13mem-ruby: Use check_on_cache_probe on MOESI CMPPouya Fotouhi
This change uses check_on_cache_probe statement to check if the cacheline subject to eviction is locked in MOESI CMP. Change-Id: I3a8879e10ebd94ef68194836475e656761fed62c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19908 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-08-13mem-ruby: Use check_on_cache_probe on MOESIPouya Fotouhi
This change uses check_on_cache_probe statement to check if the cacheline subject to eviction is locked in MOESI. Change-Id: Ie650ccdc15bb41b4088e534975b662408aaccf24 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19890 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-08-12arch-arm: Added LD/ST<op> atomic instruction family and SWP instrsJordi Vaquero
Adding LD/ST/SWP family of instructions, LD/ST include a set of operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN This commit includes: + Instruction decode + Instruction functional code + New set of skeletons for Ex/Com/Ini/Constructor and declaration. Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19812 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-08-12mem-ruby: Use check_on_cache_probe to protect locked lines from evictionPouya Fotouhi
This change uses check_on_cache_probe statement to check if the cacheline subject to eviction is locked in MESI Three Level. Change-Id: Ib0de54aa067c7603db1f7321cc4825b123b641ac Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19868 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-12mem-ruby: Use check_on_cache_probe to protect locked lines from evictionPouya Fotouhi
This change uses check_on_cache_probe statement to check if the cacheline subject to eviction is locked in MESI Two Level. Other protocols should be updated accordingly. Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Change-Id: Idcdbc8ee528eb5e4e2f8d56a268a3a92eadd95b1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16809 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-12dev-arm: Enable DTB autogeneration in GICv3Giacomo Travaglini
Change-Id: I539ae5ae74bc6f42f291441594a0d14c98e687f4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20053 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-12dev-arm: Fix PCI node's interrupt-map propertyGiacomo Travaglini
The PCI host has an interrupt-map property which only works for a fixed setup of parent/child interrupt/address cells, which currently overlaps with GICv2. We want to make this flexible, so that the interrupt-map doesn't break if we change the interrupt/address-cells value, and the patch is aiming in that direction. This is also needed for GICv3 DTB autogeneration, since it is using different values than GICv2. Change-Id: If1c661ddcbc0c277c9d6b0e44a0fd3fe2427618c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20052 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-12dev-arm: Use FdtState to generate GIC properitesGiacomo Travaglini
Rather than hardcoding property values, we use a FdtState variable, so that it is possible to retrieve them from an external object. Change-Id: Ifd90814b03c68a7f55ef3be6123dcfee5e1de568 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20051 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-12python: FdtState using interrupt-cellsGiacomo Travaglini
Change-Id: I37813748f518b442d2b53c2bc4f381edb2e26146 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20050 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-12arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic funcJordi Vaquero
CAS/CASP atomic instruction implementation This change includes: + Instructions decode + new amo64.isa file where CAS/CASP main functional code is implemented + mem64.isa include Execute/complete/initiatie skeletons, contructor and declarator + Added TypedAtomic function for pair register CASP instruction Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19811 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-08-12sim-se: rename Process::setpgid memberBrandon Potter
The getter methods to access these types of members do not have a 'get' string in the method names. To make the interface a bit more consistent, remove the 'set' part of the member name. Change-Id: I04c56bd9d9feb1cf68ff50a1152083ea57ea7c62 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20008 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-10cpu: Pull more arch specialization to the top of BaseCPU.py.Gabe Black
This simplifies the logic of the CPU python class, and brings us ever so slightly closer to factoring hardcoded ISA behavior out of non-ISA specific components. Change-Id: I7e4511dd4e6076f5c214be5af2a0e33af0142563 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19889 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-08-10x86: Move some fixed or dummy config information into X86LocalApic.py.Gabe Black
The X86 local APIC doesn't actually use the pio_addr set in the config and instead computes what address it will respond to based on the initial ID of the CPU it's attached to. gem5's BasicPioDevice, which the X86LocalApic class inherits from, does not provide a default value for that parameter and will complain if *something* isn't set. The value used, 0x2000000000000000, is a dummy value which is the base of the region of the physical address space set aside for messages to local APICs from the CPU and from other local APICs. Also, the clock for the local APIC's timer is defined to be the bus clock. The assumption seems to be that this has a 16:1 ratio with the CPU clock, and I vaguely remember finding that that was more or less unofficially true, even if it isn't necessary stringently defined to be that. Since we were already just assuming that that ratio was correct and always setting up the local APICs clock that way, we can do that in the X86LocalApic class definition and remove some special x86 specific setup that we'd otherwise need for the x86 version of the Interrupt class. If that's not correct, it can still be overridden somewhere else in the config. Change-Id: I50e84f899f44b1191c2ad79d05803b44f07001f9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19968 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-09arch: Bump MaxVecRegLenInBytes to 4096Tony Gutierrez
The GPU model uses the generic vector register containers, however the maximum vector register length is fixed at 256, which is an invalid assumption for the GPU model as it can operate on vectors up to 4096B. Change-Id: Id85e0ed45c9a9c1a4bb6e712c44eaeec2d628fce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17908 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-09sim-se: minor refactor for ProcessParams::createBrandon Potter
Remove the nullptr initialization and change the message for object file failure. Change-Id: I14b80b47b65893c55810e7f715c1b8fc643c5125 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19949 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-09sim-se: remove unused parameterBrandon Potter
The init function which processes invoke on their page tables has a thread context pointer parameter. The parameter is not used by the code so remove it. Change-Id: Ic4766fbc105d81c1c9ee4b5c0f428497dff2ab30 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19948 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-07cpu-o3: fix atomic instructions non-speculativeJordi Vaquero
Fix problem with O3 and AMO instructions. At initial stages amo instruction is considered a type of non-speculative store. After the instruction has been commited and during the squash step, acquire_release version of the AMO operation is considered speculative, that differents results in an assert fault. This fix ensures that AMO instructions are always considered non-speculative, during early stages and during squas/removal of the instruction. Change-Id: Ia0c5fbb9dc44a9991337b57eb759b1ed08e4149e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19815 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-07cpu-o3: added _amo_op parameter in o3 LSQJordi Vaquero
Fix bug with AMO (or RMW) instructions where the amo_op variable is not being propagated to the LSQ request. Change-Id: I60c59641d9b497051376f638e27f3c4cc361f615 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19814 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-08-07arch-arm: Add TypeAtomicOp class to be used by new atomic instructionsJordi Vaquero
Creating a new object TypeAtomicOp that will be used by the atomic instructions following gem5 AMO feature. Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19810 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-07arch-arm: adding register control flags enabling LSE implementationJordi Vaquero
Added changes on arch-arm architecture to accept Atomic instructions following ARM v8.1 documentation. That includes enabling atomic bit in ID registers and add have_lse variable into arm system. Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-07dev-arm: Perform SMMUv3 CFG Invalidation at device interfaceGiacomo Travaglini
In the current SMMUv3 model, multiple micro/mainTLB are present at the device interface (SMMUv3SlaveInterface), caching translations specific to a device. Those distributed TLBs are checked for a translation before checking for centralized TLBs (shared by devices), like the configuration cache, walk cache etc. This means that if a hit in these TLBs occurs, there won't be a need to enter configuration stage (which is where the STE and CD are retrieved). So if we invalidate a cached configuration (in ConfigCache), we need to invalidate those interface TLB entries as well, otherwise in theory we will keep the same translation even after a change in configuration tables. Change-Id: I4aa36ba8392a530267517bef7562318b282bee25 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel van Tol <michiel.vantol@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19813 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-07mem-cache: Fix non-virtual base destructor of Repl EntryDaniel R. Carvalho
ReplaceableEntry contains a virtual method, yet its destructor was not virtual, causing errors in some compilers. Change-Id: I13deec843f4007d9deb924882a8d98ff6a89c84f Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19808 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-06sim-se: add new getpgrp system callBrandon Potter
This changeset adds new (relatively simple) system call support. The getpgrp call returns a thread context's pgid. Change-Id: I361bdbfb9c01b761ddd5a4923d23f86971f8d614 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17111 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
2019-08-06sim-se: adding pipe2 syscallMatthew Sinclair
pipe2 builds on top of the pipe syscall implementation by adding some extra flags for the files (to avoid have to make separate calls to fcntl). Change-Id: I88cf6f1387b9d14e60b33a32db412da9ed93a3e6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12310 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-05arch-arm: Implement ARMv8.1-PAN, Privileged access neverGiacomo Travaglini
ARMv8.1-PAN adds a new bit to PSTATE. When the value of this PAN state bit is 1, any privileged data access from EL1 or EL2 to a virtual memory address that is accessible at EL0 generates a Permission fault. This feature is mandatory in ARMv8.1 implementations. This feature is supported in AArch64 and AArch32 states. The ID_AA64MMFR1_EL1.PAN, ID_MMFR3_EL1.PAN, and ID_MMFR3.PAN fields identify the support for ARMv8.1-PAN. Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Change-Id: I94a76311711739dd2394c72944d88ba9321fd159 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19729 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-05arch-arm: Rewrite MSR immediate instruction classGiacomo Travaglini
MSR <pstatefield>, #imm is used for setting a PSTATE field using an immediate. Current implementation has the following flaws: * There is no base MSR immediate definition: all the existing PSTATE fields have a different class definition * Those implementation make use of a generic data64 base class which results in a wrong disassembly (pstate register is printed as an integer register). This patch is fixing this by defining a new base class (MiscRegImmOp64) and new related templates. In this way, we aim to ease addition of new PSTATE fields (in ARMv8.x) Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19728 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-05systemc: Provide Port wrapper classes for sc_portChun-Chen TK Hsu
Add Port wrappers for sc_port, sc_interface, and sc_export. Change-Id: Ib70cb7466461c8d32e3a260bf2a2d60a6ded87c3 Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19788 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-02mem-ruby: Remove assertion with incorrect assumptionPouya Fotouhi
Current code assumes that only one cacheline would either be in RW. This is not true for GPU protocols, and may not be true for some CPU-only protocols with state violations. Change-Id: I70db4fbb4e80663551e8635307bb937a4db8dc63 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19708 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-02sim-se: small refactor on pipe syscallBrandon Potter
Change-Id: I02ffb1c4af980554ff12ac7d11d32ba80fe261c5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12308 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-02mem: Move eraseIfNullEntry to when holder is updatedDaniel R. Carvalho
The entry should only be tested for deletion when holder is updated. Change-Id: I5a10b6fa876912709b7467860d43c23c60f38568 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19750 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-02 19:36:37 +0000