summaryrefslogtreecommitdiff
path: root/system/arm/dt
AgeCommit message (Collapse)Author
2020-01-14system-arm: bigLITTLE with VExpress_GEM5_V2 in dtbAdrian Herrera
This patch adds targets in the device tree Makefile for using bigLITTLE DTS with VExpress_GEM5_V2 platform. Change-Id: I7a424a36c78a24b96224526aa112ac5d060f790b Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24083 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-20system-arm: Use dts include instead of cpp in ARM DTBsBertrand Marquis
Change-Id: I342691a42e84dfe53659a7acb3b8db04e52e3002 Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22824 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-18system-arm: Add ITS node in platforms/vexpress_gem5_v2_base.dtsiAdrian Herrera
This is aligning sources with DTB autogeneration Change-Id: Icf369eb85719c91da770398b45645d8b03d8abf3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20982 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-22dev-arm,system-arm: missing GICv3 ranges propertyAdrian Herrera
This patch adds the device tree "ranges" property to GICv3 for the VExpress_GEM5_V2 platform. It is also included in the GICv3 DTB auto generation. This allows the GICv3 ITS to be specified in the device tree. Change-Id: I00e1bb0fd45521e34820c0a23ddf047afec7aa4c Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20255 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-10system-arm: Refactor makefile to create targets with functionsChun-Chen TK Hsu
This change simplifies writing targets which has same prefix but differrent number of CPUs. Change-Id: I3b7d67a554f5d27714ace6b88c9784ddaa3b34d5 Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19989 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-07-30system-arm: Add irq for hypervisor timer in device treeChun-Chen TK Hsu
ARM fast model CPU cannot get timer interrupts without this IRQ setting in the device tree. Change-Id: I084c475c04285f4f40eb38a80ddd038207e4764f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19650 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-25dev-arm: Limit number of max PE in GICv3 to 128Giacomo Travaglini
This is needed since there is a problem in the memory layout of VExpress_GEM5_V2 as it is: having 256KB pages is creating overlapping regions when reserving space for 256 PEs. GICv3 redistributors: 0x2c010000 - 0x30010000 PCI regions: 0x30000000 - 0x40000000 We fix this by cutting down the number of supported PEs to 128 Change-Id: I6e87f66a6150a441ccba298662b4548a4972dc40 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18392 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-02-12system-arm: Fix dtsi dependencies in MakefileKevin Brodsky
Making vexpress_gem5_vX.dtsi depend on vexpress_gem5_vX_base.dtsi does nothing, since vexpress_gem5_vX.dtsi is never built (much in the same way as there is no point in making a C header depend on another). Fix that by making all the .dts depend on both .dtsi's. Change-Id: I9131e0b1b2e521bb09d14721dec38bf6a2d98583 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Ruben Ayrapetyan <ruben.ayrapetyan@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16143 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-07system-arm: Add device tree for new VExpress GEM5_V2 platformJairo Balart
Change-Id: Ifc2b91afe5b88a656b4ed1c64ab6cca97f082034 Reviewed-on: https://gem5-review.googlesource.com/c/14275 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-14system-arm: Split the VExpress_GEM5_V1 base dtsAndreas Sandberg
With the introduction of the new DPU model, we need different variations of the VExpress_GEM5_V1 platform. This splits the platform dtsi file into a separate file for the base platform and the HDLCD-based platform. This matches the hierarchy in RealView.py. Change-Id: Id02380122655b5d3aa3548a703fdef178bba17d9 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11035 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-07dev-arm: Add a VirtIO MMIO device to VExpress_GEM5_V1Andreas Sandberg
Add an ARM-specific VirtIO MMIO device to the VExpress_GEM5_V1 platform. Change-Id: Id1e75398e039aad9d637f46f653cda9084d3d2fe Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2327
2018-06-06system-arm: Update gem5 timer interrupt specificationAndreas Sandberg
The DTB for the VExpress_GEM5_V1 was incorrectly flagging timer interrupts as being edge triggered. Describe the interrupt as being level triggered to match Juno and FVP. Change-Id: I9ce4b8959e7cc28d8b208727119ff20e581311f8 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10024 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2016-07-21arm, config: Add an example ARM big.LITTLE(tm) configuration scriptGabor Dozsa
An ARM big.LITTLE system consists of two cpu clusters: the big CPUs are typically complex out-of-order cores and the little CPUs are simpler in-order ones. The fs_bigLITTLE.py script can run a full system simulation with various number of big and little cores and cache hierarchy. The commit also includes two example device tree files for booting Linux on the bigLITTLE system. Change-Id: I6396fb3b2d8f27049ccae49d8666d643b66c088b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-06arm: Update dts to work with the new HDLCD driverAndreas Sandberg
The dts files in system/arm/dt currently assume that an (unreleased) gem5-specific virtual encoder is used as a remote endpoint for the HDLCD. This driver won't be released as a more general virtual encoder is about to be posted on the Linux DRI devel list and this encoder has now been merged with gem5's kernel tree. This changeset updates gem5's dts files to use that encoder. Change-Id: Ic1a1be728efd31603752fdfba005b6dbdea42e7e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Rene De Jong <rene.dejong@arm.com>
2016-02-23arm: Ship Linux device trees with gem5Andreas Sandberg
Ship aarch32 and aarch64 device trees with gem5. We currently ship device trees as a part of the gem5 Linux kernel repository. This makes tracking hard since device trees are supposed to be platform dependent rather than kernel dependent (Linux considers device trees to be a stable kernel ABI). It also makes code sharing between aarch32 and aarch64 impossible. This changeset implements a set of device trees for the new VExpress_GEM5_V1 platform. The platform is described in a shared file that is separate from the memory/CPU description. Due to differences in how secondary CPUs are initialized, aarch32 and aarch64 use different base files describing CPU nodes and the machine's compatibility property.
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-19 10:41:23 +0000