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2019-10-09system-arm: Initialize ICC_SRE_EL3 register of all CPUsChun-Chen TK Hsu
Fix a bug that only CPU0 initialized ICC_SRE_EL3 register. Change-Id: I625c9a25bada80b864e5eb5a8b8be14ee324b801 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21539 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-09-18system-arm: Add ITS node in platforms/vexpress_gem5_v2_base.dtsiAdrian Herrera
This is aligning sources with DTB autogeneration Change-Id: Icf369eb85719c91da770398b45645d8b03d8abf3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20982 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-22dev-arm,system-arm: missing GICv3 ranges propertyAdrian Herrera
This patch adds the device tree "ranges" property to GICv3 for the VExpress_GEM5_V2 platform. It is also included in the GICv3 DTB auto generation. This allows the GICv3 ITS to be specified in the device tree. Change-Id: I00e1bb0fd45521e34820c0a23ddf047afec7aa4c Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20255 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-10system-arm: Refactor makefile to create targets with functionsChun-Chen TK Hsu
This change simplifies writing targets which has same prefix but differrent number of CPUs. Change-Id: I3b7d67a554f5d27714ace6b88c9784ddaa3b34d5 Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19989 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-07-30system-arm: Add irq for hypervisor timer in device treeChun-Chen TK Hsu
ARM fast model CPU cannot get timer interrupts without this IRQ setting in the device tree. Change-Id: I084c475c04285f4f40eb38a80ddd038207e4764f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19650 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-07-30system-arm: Initialize ICC_SRE_EL3 registerChun-Chen TK Hsu
Fast model CPU will throw exceptions if ICC_SRE_EL3 is not initialized before accessing other interrupt controller system registers. Change-Id: I638f77aa7a3a4ad92abf2554d039c37601fbd44f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19649 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-25dev-arm: Limit number of max PE in GICv3 to 128Giacomo Travaglini
This is needed since there is a problem in the memory layout of VExpress_GEM5_V2 as it is: having 256KB pages is creating overlapping regions when reserving space for 256 PEs. GICv3 redistributors: 0x2c010000 - 0x30010000 PCI regions: 0x30000000 - 0x40000000 We fix this by cutting down the number of supported PEs to 128 Change-Id: I6e87f66a6150a441ccba298662b4548a4972dc40 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18392 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-02-12system-arm: Fix dtsi dependencies in MakefileKevin Brodsky
Making vexpress_gem5_vX.dtsi depend on vexpress_gem5_vX_base.dtsi does nothing, since vexpress_gem5_vX.dtsi is never built (much in the same way as there is no point in making a C header depend on another). Fix that by making all the .dts depend on both .dtsi's. Change-Id: I9131e0b1b2e521bb09d14721dec38bf6a2d98583 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Ruben Ayrapetyan <ruben.ayrapetyan@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16143 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-07system-arm: Add device tree for new VExpress GEM5_V2 platformJairo Balart
Change-Id: Ifc2b91afe5b88a656b4ed1c64ab6cca97f082034 Reviewed-on: https://gem5-review.googlesource.com/c/14275 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-07system-arm: Add aarch64 bootloader support for GICv3Jairo Balart
Change-Id: If75262709868cc59d320f60273a32397339f1dd5 Signed-off-by: Jairo Balart <jairo.balart@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/13435 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-14system-arm: Split the VExpress_GEM5_V1 base dtsAndreas Sandberg
With the introduction of the new DPU model, we need different variations of the VExpress_GEM5_V1 platform. This splits the platform dtsi file into a separate file for the base platform and the HDLCD-based platform. This matches the hierarchy in RealView.py. Change-Id: Id02380122655b5d3aa3548a703fdef178bba17d9 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11035 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-07dev-arm: Add a VirtIO MMIO device to VExpress_GEM5_V1Andreas Sandberg
Add an ARM-specific VirtIO MMIO device to the VExpress_GEM5_V1 platform. Change-Id: Id1e75398e039aad9d637f46f653cda9084d3d2fe Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2327
2018-06-06system-arm: Update gem5 timer interrupt specificationAndreas Sandberg
The DTB for the VExpress_GEM5_V1 was incorrectly flagging timer interrupts as being edge triggered. Describe the interrupt as being level triggered to match Juno and FVP. Change-Id: I9ce4b8959e7cc28d8b208727119ff20e581311f8 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10024 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2017-11-16system-arm: change system/arm/aarch64_bootloader/boot.S copyrightJose Marinho
The aarch64 boot loader was distributed using a BSD license that was using non-standard formatting. Updated the license to match gem5's canonical license format and removed the separete LICENSE.txt file. Change-Id: I660b73ca5ddd922763a2b72051c73d539248ebcf Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5728 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2016-07-21arm, config: Add an example ARM big.LITTLE(tm) configuration scriptGabor Dozsa
An ARM big.LITTLE system consists of two cpu clusters: the big CPUs are typically complex out-of-order cores and the little CPUs are simpler in-order ones. The fs_bigLITTLE.py script can run a full system simulation with various number of big and little cores and cache hierarchy. The commit also includes two example device tree files for booting Linux on the bigLITTLE system. Change-Id: I6396fb3b2d8f27049ccae49d8666d643b66c088b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-06arm: Update dts to work with the new HDLCD driverAndreas Sandberg
The dts files in system/arm/dt currently assume that an (unreleased) gem5-specific virtual encoder is used as a remote endpoint for the HDLCD. This driver won't be released as a more general virtual encoder is about to be posted on the Linux DRI devel list and this encoder has now been merged with gem5's kernel tree. This changeset updates gem5's dts files to use that encoder. Change-Id: Ic1a1be728efd31603752fdfba005b6dbdea42e7e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Rene De Jong <rene.dejong@arm.com>
2016-02-23arm: Ship Linux device trees with gem5Andreas Sandberg
Ship aarch32 and aarch64 device trees with gem5. We currently ship device trees as a part of the gem5 Linux kernel repository. This makes tracking hard since device trees are supposed to be platform dependent rather than kernel dependent (Linux considers device trees to be a stable kernel ABI). It also makes code sharing between aarch32 and aarch64 impossible. This changeset implements a set of device trees for the new VExpress_GEM5_V1 platform. The platform is described in a shared file that is separate from the memory/CPU description. Due to differences in how secondary CPUs are initialized, aarch32 and aarch64 use different base files describing CPU nodes and the machine's compatibility property.
2016-02-06style: remove trailing whitespaceSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-white -a'.
2015-07-15arm: Bootloader fix for v8 over 16 coresKarthik Sangaiah
Previous code used a smaller 4 bit mask to test the MPIDR-EL1 register. The bitmask was extended to support greater than 16 cores.
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
2012-09-07ARM: Fix issue with with way MPIDR is read to include affinity levels.Matt Evans
The simple_bootloader checks for CPU0 in a manner incompatible with systems actually using affinity levels -- just looking at MPIDR[7:0]. However, in future we may wish to use real affinity levels and this method will be in danger of matching several CPUs with affinity0 = 0. Match affinity2 == affinity1 == affinity0 == 0 instead.
2012-03-01ARM: Add support for Versatile Express extended memory mapAli Saidi
Also clean up how we create boot loader memory a bit.
2011-05-04ARM: Boot loader changes that make it more flexible about load and I/O addrsPrakash Ramrakhyani
2011-02-16Cleanup system directory to fit into modern M5 treeNathan Binkert
2011-02-16copyright: update copyright on alpha system filesNathan Binkert
2007-10-19Fix bug in MDT BITMAP to allow more than 2GB of memory.Geoffrey Blake
Signed-off by Ali Saidi <saidi@eecs.umich.edu>
2006-08-16fix Makefile for new source treeAli Saidi
2006-08-16update our copyrights to the new formatAli Saidi
2006-04-26put panic instructions in palcode rather than looping on mchecks.Ali Saidi
2006-02-28Add m5op to the build processAli Saidi
use quiesceNs on other CPUs panic rather than spin on an error console/Makefile: Add m5op to the build process console/dbmentry.S: use quiesceNs on other CPUs console/printf.c: panic rather than spin on an error.
2006-02-23change from bootStrap* to using the cpuStack array for setting upAli Saidi
other processor stacks
2005-08-18Fix console to work on all systems.Nathan Binkert
console/console.c: CONS_REM (remote console) doesn't work on Tru64. Use CONS_DZ which seems to work alright everywhere.
2005-07-28Merge zed.eecs.umich.edu:/.automount/fox/y/mserrano/alpha-systemBenjamin Nash
into zed.eecs.umich.edu:/z/benash/bk/alpha-system console/console.c: Clean up code. h/rpb.h: Update CTB struct.
2005-07-28changesMiguel Serrano
console/console.c: fixed bootstrap stack h/rpb.h: ctb_term_type instead of ctb_baud
2005-07-26Merge m5read@m5.eecs.umich.edu:/bk/alpha-systemBenjamin Nash
into zed.eecs.umich.edu:/z/benash/bk/alpha-system
2005-07-26New console terminal block structure, fix kernel stack pointer.Benjamin Nash
console/console.c: Use virtual addresses for kernel stack pointer, use new ctb structure. h/rpb.h: Update console terminal block structure.
2005-06-29Add missing TSUNAMI ipi code.Nathan Binkert
2005-06-28console code cleanupNathan Binkert
console/console.c: the go parameter to unixBoot is never used, so get rid of it. just panic if we return from unixBoot since it's never supposed to happen. remove the MAX_CPUS parameter and the bootStrapImpure variable and just allocate memory as needed. (Can in theory support many more CPUs.)
2005-06-28pass the location of the m5 backdoor via the m5AlphaAccess variableNathan Binkert
only compile one console console/Makefile: Now that the location of the m5 backdoor is passed into the console via the m5AlphaAccess variable, we only need to compile one console, and don't need to define TLASER or TSUNAMI console/console.c: Don't hardcode the location of the AlphaAccess structure, but rely on m5 to pass in the correct value. Setup "volatile struct AlphaAccess *m5AlphaAccess" for use and get rid of the hardcoded usage.
2005-06-27Add tlaser.h, required by platform.SNathan Binkert
2005-06-27Major system code cleanup and formattingNathan Binkert
remove unused code console/Makefile: cleanup Makefile. Remove unneeded -D options console/console.c: Major cleanup and formatting remove unused #ifdef code remove unused #includes rename xxm -> m5 rename simos -> m5 console/dbmentry.S: console/paljtokern.S: console/paljtoslave.S: console/printf.c: Major cleanup and formatting remove unused #ifdef code remove unused #includes rename __start -> _start to get rid of warning. h/cserve.h: h/dc21164FromGasSources.h: h/ev5_alpha_defs.h: h/ev5_defs.h: h/ev5_osfalpha_defs.h: h/ev5_paldef.h: h/fromHudsonMacros.h: h/fromHudsonOsf.h: h/rpb.h: Major cleanup and formatting h/ev5_impure.h: Major cleanup and formatting remove unused #ifdef code palcode/Makefile: cleanup Makefile remove unused -D options unify platform_tlaser.S and platform_tsunami.S into platform.S and generate multiple .o files using various #defines unify osfpal.S osfpal_cache_copy.S and osfpal_cache_copy_unaligned.S into osfpal.S and generate multiple .o files using various #defines palcode/osfpal.S: Major cleanup and formatting remove unused #defines remove unused #if code merge copy code into this file. palcode/platform.S: Major cleanup and formatting remove unused #defines remove unused #if code merge platform code into this file.
2005-06-04HP copyrightsAli Saidi
console/Makefile: Added copyright added CROSS_COMPILE variable removed install target console/console.c: console/dbmentry.S: console/paljtokern.S: console/paljtoslave.S: console/printf.c: h/cia.h: h/cserve.h: h/dc21164FromGasSources.h: h/eb164.h: h/ev5_alpha_defs.h: h/ev5_defs.h: h/ev5_impure.h: h/ev5_osfalpha_defs.h: h/ev5_paldef.h: h/fromHudsonMacros.h: h/fromHudsonOsf.h: h/lib.h: h/platform.h: h/regdefs.h: h/rpb.h: palcode/Makefile: palcode/osfpal.S: palcode/osfpal_cache_copy.S: palcode/osfpal_cache_copy_unaligned.S: palcode/platform_m5.S: palcode/platform_tlaser.S: added hp and our copyright
2005-01-30removed tlaserreg.h, rewrote necessary partsAli Saidi
deleted simos.h deleted tlaserreg.h palcode/platform_m5.S: palcode/platform_tlaser.S: removed tlaserreg.h, rewrote necessary parts
2004-12-06Add support for tsunami with 64 processors and fix some console bugsAli Saidi
I steped on while doing it console/console.c: Allocate more HWRPB pages so we have room for 64 percpu_rpbs Fix writing of Console Relocation Block virtual addresses so that if they are outside of the first page, which they will be with more than 8 processors, the correct adress is written palcode/Makefile: Update makefile for tsunami with 64 processors palcode/platform_m5.S: Add support for tsunami with 64 processors
2004-11-23do a better job of always locking printf. We used to only lock onAli Saidi
secondary cpus, this also locks on the primary cpu. Now the initial print out doesn't get garbled with more than 1 cpu.
2004-11-23Makefile cleanup, no seperate middle preprocessing steps anymoreAli Saidi
2004-11-23cleanup makefile and fix platform bug introduced in last commitAli Saidi
palcode/Makefile: Cleanup make file, no more ugly preprocessing steps palcode/platform_m5.S: fix a mistake with m5 platform cleanup from before
2004-11-23update platform code to use PALTemp Whami register to get cpu idAli Saidi
instead of reading register from tsunami chipset, saving an uncached read
2004-10-06Fix from Adam: Strip the kseg off the physical address in the RPB structure.Ali Saidi
2004-09-01changes to make smp work in linuxAli Saidi
console/console.c: Remove Printed SimOS references and replace with M5 Rework the SMP stuff, so we don't trash any stacks, or what we thought were stacks, but are actually other ppls memory. console/dbmentry.s: add a carefully crafted piece of assembly that doesn't use the stack, so we don't clobber anthing in the time between when we are spinning and when the OS tells us to go. palcode/platform_m5.s: add/fix code for IPI, multiprocessor interrupts (DIR), and initial bootstrapping of the cpu
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