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With the introduction of the new DPU model, we need different
variations of the VExpress_GEM5_V1 platform. This splits the platform
dtsi file into a separate file for the base platform and the
HDLCD-based platform. This matches the hierarchy in RealView.py.
Change-Id: Id02380122655b5d3aa3548a703fdef178bba17d9
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11035
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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Add an ARM-specific VirtIO MMIO device to the VExpress_GEM5_V1
platform.
Change-Id: Id1e75398e039aad9d637f46f653cda9084d3d2fe
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2327
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The DTB for the VExpress_GEM5_V1 was incorrectly flagging timer
interrupts as being edge triggered. Describe the interrupt as being
level triggered to match Juno and FVP.
Change-Id: I9ce4b8959e7cc28d8b208727119ff20e581311f8
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10024
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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The aarch64 boot loader was distributed using a BSD license that was
using non-standard formatting. Updated the license to match gem5's
canonical license format and removed the separete LICENSE.txt file.
Change-Id: I660b73ca5ddd922763a2b72051c73d539248ebcf
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5728
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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An ARM big.LITTLE system consists of two cpu clusters: the big
CPUs are typically complex out-of-order cores and the little
CPUs are simpler in-order ones. The fs_bigLITTLE.py script
can run a full system simulation with various number of big
and little cores and cache hierarchy. The commit also includes
two example device tree files for booting Linux on the
bigLITTLE system.
Change-Id: I6396fb3b2d8f27049ccae49d8666d643b66c088b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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The dts files in system/arm/dt currently assume that an (unreleased)
gem5-specific virtual encoder is used as a remote endpoint for the
HDLCD. This driver won't be released as a more general virtual encoder
is about to be posted on the Linux DRI devel list and this encoder has
now been merged with gem5's kernel tree. This changeset updates gem5's
dts files to use that encoder.
Change-Id: Ic1a1be728efd31603752fdfba005b6dbdea42e7e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Rene De Jong <rene.dejong@arm.com>
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Ship aarch32 and aarch64 device trees with gem5. We currently ship
device trees as a part of the gem5 Linux kernel repository. This makes
tracking hard since device trees are supposed to be platform dependent
rather than kernel dependent (Linux considers device trees to be a
stable kernel ABI). It also makes code sharing between aarch32 and
aarch64 impossible.
This changeset implements a set of device trees for the new
VExpress_GEM5_V1 platform. The platform is described in a shared file
that is separate from the memory/CPU description. Due to differences
in how secondary CPUs are initialized, aarch32 and aarch64 use
different base files describing CPU nodes and the machine's
compatibility property.
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Result of running 'hg m5style --skip-all --fix-white -a'.
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Previous code used a smaller 4 bit mask to test the MPIDR-EL1 register.
The bitmask was extended to support greater than 16 cores.
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Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.
Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
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The simple_bootloader checks for CPU0 in a manner incompatible with systems
actually using affinity levels -- just looking at MPIDR[7:0]. However, in
future we may wish to use real affinity levels and this method will be in danger
of matching several CPUs with affinity0 = 0.
Match affinity2 == affinity1 == affinity0 == 0 instead.
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Also clean up how we create boot loader memory a bit.
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Signed-off by Ali Saidi <saidi@eecs.umich.edu>
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use quiesceNs on other CPUs
panic rather than spin on an error
console/Makefile:
Add m5op to the build process
console/dbmentry.S:
use quiesceNs on other CPUs
console/printf.c:
panic rather than spin on an error.
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other processor stacks
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console/console.c:
CONS_REM (remote console) doesn't work on Tru64. Use CONS_DZ which
seems to work alright everywhere.
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into zed.eecs.umich.edu:/z/benash/bk/alpha-system
console/console.c:
Clean up code.
h/rpb.h:
Update CTB struct.
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console/console.c:
fixed bootstrap stack
h/rpb.h:
ctb_term_type instead of ctb_baud
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into zed.eecs.umich.edu:/z/benash/bk/alpha-system
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console/console.c:
Use virtual addresses for kernel stack pointer, use new ctb structure.
h/rpb.h:
Update console terminal block structure.
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console/console.c:
the go parameter to unixBoot is never used, so get rid of it.
just panic if we return from unixBoot since it's never supposed
to happen.
remove the MAX_CPUS parameter and the bootStrapImpure variable
and just allocate memory as needed. (Can in theory support many
more CPUs.)
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only compile one console
console/Makefile:
Now that the location of the m5 backdoor is passed into the
console via the m5AlphaAccess variable, we only need to
compile one console, and don't need to define TLASER or TSUNAMI
console/console.c:
Don't hardcode the location of the AlphaAccess structure, but
rely on m5 to pass in the correct value.
Setup "volatile struct AlphaAccess *m5AlphaAccess" for use and
get rid of the hardcoded usage.
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remove unused code
console/Makefile:
cleanup Makefile. Remove unneeded -D options
console/console.c:
Major cleanup and formatting
remove unused #ifdef code
remove unused #includes
rename xxm -> m5
rename simos -> m5
console/dbmentry.S:
console/paljtokern.S:
console/paljtoslave.S:
console/printf.c:
Major cleanup and formatting
remove unused #ifdef code
remove unused #includes
rename __start -> _start to get rid of warning.
h/cserve.h:
h/dc21164FromGasSources.h:
h/ev5_alpha_defs.h:
h/ev5_defs.h:
h/ev5_osfalpha_defs.h:
h/ev5_paldef.h:
h/fromHudsonMacros.h:
h/fromHudsonOsf.h:
h/rpb.h:
Major cleanup and formatting
h/ev5_impure.h:
Major cleanup and formatting
remove unused #ifdef code
palcode/Makefile:
cleanup Makefile
remove unused -D options
unify platform_tlaser.S and platform_tsunami.S into platform.S and
generate multiple .o files using various #defines
unify osfpal.S osfpal_cache_copy.S and osfpal_cache_copy_unaligned.S into
osfpal.S and generate multiple .o files using various #defines
palcode/osfpal.S:
Major cleanup and formatting
remove unused #defines
remove unused #if code
merge copy code into this file.
palcode/platform.S:
Major cleanup and formatting
remove unused #defines
remove unused #if code
merge platform code into this file.
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console/Makefile:
Added copyright
added CROSS_COMPILE variable
removed install target
console/console.c:
console/dbmentry.S:
console/paljtokern.S:
console/paljtoslave.S:
console/printf.c:
h/cia.h:
h/cserve.h:
h/dc21164FromGasSources.h:
h/eb164.h:
h/ev5_alpha_defs.h:
h/ev5_defs.h:
h/ev5_impure.h:
h/ev5_osfalpha_defs.h:
h/ev5_paldef.h:
h/fromHudsonMacros.h:
h/fromHudsonOsf.h:
h/lib.h:
h/platform.h:
h/regdefs.h:
h/rpb.h:
palcode/Makefile:
palcode/osfpal.S:
palcode/osfpal_cache_copy.S:
palcode/osfpal_cache_copy_unaligned.S:
palcode/platform_m5.S:
palcode/platform_tlaser.S:
added hp and our copyright
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deleted simos.h
deleted tlaserreg.h
palcode/platform_m5.S:
palcode/platform_tlaser.S:
removed tlaserreg.h, rewrote necessary parts
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I steped on while doing it
console/console.c:
Allocate more HWRPB pages so we have room for 64 percpu_rpbs
Fix writing of Console Relocation Block virtual addresses so that
if they are outside of the first page, which they will be with more
than 8 processors, the correct adress is written
palcode/Makefile:
Update makefile for tsunami with 64 processors
palcode/platform_m5.S:
Add support for tsunami with 64 processors
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secondary cpus, this also locks on the primary cpu.
Now the initial print out doesn't get garbled with more than 1 cpu.
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palcode/Makefile:
Cleanup make file, no more ugly preprocessing steps
palcode/platform_m5.S:
fix a mistake with m5 platform cleanup from before
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instead of reading register from tsunami chipset, saving an uncached
read
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console/console.c:
Remove Printed SimOS references and replace with M5
Rework the SMP stuff, so we don't trash any stacks, or what we
thought were stacks, but are actually other ppls memory.
console/dbmentry.s:
add a carefully crafted piece of assembly that doesn't use the stack,
so we don't clobber anthing in the time between when we are spinning
and when the OS tells us to go.
palcode/platform_m5.s:
add/fix code for IPI, multiprocessor interrupts (DIR), and initial
bootstrapping of the cpu
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addresses so the uncachable bit is set for tsunami.
console/Makefile:
console/console.c:
changed to generate tlaser and tsunami console code at different addresses
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measure. The rest of the registers I used are touched by the tlaser
platform code so I would guess their are fair game.
Random memory troubles hopefully over.
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time. Easiest way to deal with the endian issue.
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instruction.
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console/Makefile:
palcode/Makefile:
moved header files to /h so updated make file for that
console/dbmentry.s:
console/paljtokern.s:
console/paljtoslave.s:
upadated to use osf file that the palcode uses, one less file
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directory
console/dbmentry.s:
console/printf.c:
removed unneeded includes
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into zeep.eecs.umich.edu:/.automount/zizzer/y/saidi/work/alpha-system
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