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Previous code used a smaller 4 bit mask to test the MPIDR-EL1 register.
The bitmask was extended to support greater than 16 cores.
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Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.
Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
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The simple_bootloader checks for CPU0 in a manner incompatible with systems
actually using affinity levels -- just looking at MPIDR[7:0]. However, in
future we may wish to use real affinity levels and this method will be in danger
of matching several CPUs with affinity0 = 0.
Match affinity2 == affinity1 == affinity0 == 0 instead.
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Also clean up how we create boot loader memory a bit.
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Signed-off by Ali Saidi <saidi@eecs.umich.edu>
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use quiesceNs on other CPUs
panic rather than spin on an error
console/Makefile:
Add m5op to the build process
console/dbmentry.S:
use quiesceNs on other CPUs
console/printf.c:
panic rather than spin on an error.
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other processor stacks
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console/console.c:
CONS_REM (remote console) doesn't work on Tru64. Use CONS_DZ which
seems to work alright everywhere.
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into zed.eecs.umich.edu:/z/benash/bk/alpha-system
console/console.c:
Clean up code.
h/rpb.h:
Update CTB struct.
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console/console.c:
fixed bootstrap stack
h/rpb.h:
ctb_term_type instead of ctb_baud
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into zed.eecs.umich.edu:/z/benash/bk/alpha-system
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console/console.c:
Use virtual addresses for kernel stack pointer, use new ctb structure.
h/rpb.h:
Update console terminal block structure.
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console/console.c:
the go parameter to unixBoot is never used, so get rid of it.
just panic if we return from unixBoot since it's never supposed
to happen.
remove the MAX_CPUS parameter and the bootStrapImpure variable
and just allocate memory as needed. (Can in theory support many
more CPUs.)
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only compile one console
console/Makefile:
Now that the location of the m5 backdoor is passed into the
console via the m5AlphaAccess variable, we only need to
compile one console, and don't need to define TLASER or TSUNAMI
console/console.c:
Don't hardcode the location of the AlphaAccess structure, but
rely on m5 to pass in the correct value.
Setup "volatile struct AlphaAccess *m5AlphaAccess" for use and
get rid of the hardcoded usage.
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remove unused code
console/Makefile:
cleanup Makefile. Remove unneeded -D options
console/console.c:
Major cleanup and formatting
remove unused #ifdef code
remove unused #includes
rename xxm -> m5
rename simos -> m5
console/dbmentry.S:
console/paljtokern.S:
console/paljtoslave.S:
console/printf.c:
Major cleanup and formatting
remove unused #ifdef code
remove unused #includes
rename __start -> _start to get rid of warning.
h/cserve.h:
h/dc21164FromGasSources.h:
h/ev5_alpha_defs.h:
h/ev5_defs.h:
h/ev5_osfalpha_defs.h:
h/ev5_paldef.h:
h/fromHudsonMacros.h:
h/fromHudsonOsf.h:
h/rpb.h:
Major cleanup and formatting
h/ev5_impure.h:
Major cleanup and formatting
remove unused #ifdef code
palcode/Makefile:
cleanup Makefile
remove unused -D options
unify platform_tlaser.S and platform_tsunami.S into platform.S and
generate multiple .o files using various #defines
unify osfpal.S osfpal_cache_copy.S and osfpal_cache_copy_unaligned.S into
osfpal.S and generate multiple .o files using various #defines
palcode/osfpal.S:
Major cleanup and formatting
remove unused #defines
remove unused #if code
merge copy code into this file.
palcode/platform.S:
Major cleanup and formatting
remove unused #defines
remove unused #if code
merge platform code into this file.
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console/Makefile:
Added copyright
added CROSS_COMPILE variable
removed install target
console/console.c:
console/dbmentry.S:
console/paljtokern.S:
console/paljtoslave.S:
console/printf.c:
h/cia.h:
h/cserve.h:
h/dc21164FromGasSources.h:
h/eb164.h:
h/ev5_alpha_defs.h:
h/ev5_defs.h:
h/ev5_impure.h:
h/ev5_osfalpha_defs.h:
h/ev5_paldef.h:
h/fromHudsonMacros.h:
h/fromHudsonOsf.h:
h/lib.h:
h/platform.h:
h/regdefs.h:
h/rpb.h:
palcode/Makefile:
palcode/osfpal.S:
palcode/osfpal_cache_copy.S:
palcode/osfpal_cache_copy_unaligned.S:
palcode/platform_m5.S:
palcode/platform_tlaser.S:
added hp and our copyright
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deleted simos.h
deleted tlaserreg.h
palcode/platform_m5.S:
palcode/platform_tlaser.S:
removed tlaserreg.h, rewrote necessary parts
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I steped on while doing it
console/console.c:
Allocate more HWRPB pages so we have room for 64 percpu_rpbs
Fix writing of Console Relocation Block virtual addresses so that
if they are outside of the first page, which they will be with more
than 8 processors, the correct adress is written
palcode/Makefile:
Update makefile for tsunami with 64 processors
palcode/platform_m5.S:
Add support for tsunami with 64 processors
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secondary cpus, this also locks on the primary cpu.
Now the initial print out doesn't get garbled with more than 1 cpu.
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palcode/Makefile:
Cleanup make file, no more ugly preprocessing steps
palcode/platform_m5.S:
fix a mistake with m5 platform cleanup from before
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instead of reading register from tsunami chipset, saving an uncached
read
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console/console.c:
Remove Printed SimOS references and replace with M5
Rework the SMP stuff, so we don't trash any stacks, or what we
thought were stacks, but are actually other ppls memory.
console/dbmentry.s:
add a carefully crafted piece of assembly that doesn't use the stack,
so we don't clobber anthing in the time between when we are spinning
and when the OS tells us to go.
palcode/platform_m5.s:
add/fix code for IPI, multiprocessor interrupts (DIR), and initial
bootstrapping of the cpu
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addresses so the uncachable bit is set for tsunami.
console/Makefile:
console/console.c:
changed to generate tlaser and tsunami console code at different addresses
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measure. The rest of the registers I used are touched by the tlaser
platform code so I would guess their are fair game.
Random memory troubles hopefully over.
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time. Easiest way to deal with the endian issue.
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instruction.
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console/Makefile:
palcode/Makefile:
moved header files to /h so updated make file for that
console/dbmentry.s:
console/paljtokern.s:
console/paljtoslave.s:
upadated to use osf file that the palcode uses, one less file
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directory
console/dbmentry.s:
console/printf.c:
removed unneeded includes
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into zeep.eecs.umich.edu:/.automount/zizzer/y/saidi/work/alpha-system
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console/Makefile:
Updated to build on linux and removed
lots of crud that compiled, disassembled, and then reassembled
console/dbmentry.s:
the assembler didn't like they comments, so I removed them
console/printf.c:
Gcc was very unhappy, so I fixed this line
h/lib.h:
time_t is defined in a std header, and this was causing some problems
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palcode/osfpal.s:
Add copypal loop copy implementation.
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deleted and then upon realizing we needed them undeleted a bunch of
header files in the palcode dir
console/Makefile:
fixed so it will work with tru64... still haven't got the console to build under linux
palcode/platform_m5.s:
fixed code to "fake" srm console interrupt handling correctly
include serial interrupts
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console/console.c:
0 the system type, let m5 overwrite
palcode/platform_m5.s:
add some comments and make the timer interrupt actually care what CPU it happened on
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Now reads the MISC register to handle interrupts from multiple CPUs
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