gem5 - gem5

Age	Commit message (Expand)	Author
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-10-15	Configs: Set the memtest clock to a reasonable value	Andreas Hansson
2012-09-25	Cache: add a response latency to the caches	Mrinmoy Ghosh
2012-07-12	Mem: Make SimpleMemory single ported	Andreas Hansson
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-12	mem: fix cache stats to use request ids correctly	Dam Sunwoo
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2011-03-17	Mem: Fix issue with dirty block being lost when entire block transferred to n...	Ali Saidi
2010-02-23	cache: Make caches sharing aware and add occupancy stats.	Lisa Hsu
2007-06-30	Get rid of remaining traces of obsolete CoherenceProtocol object.	Steve Reinhardt
2007-05-19	PhysicalMemory has vector of uniform ports instead of one special one.	Steve Reinhardt
2007-05-10	remove hit_latency and make latency do the right thing	Ali Saidi
2007-02-06	Add short memtest run to quick regressions.	Steve Reinhardt
2006-10-19	Fix corner case on assertion.	Ron Dreslinski
2006-10-11	Interesting memtest finally.	Ron Dreslinski
2006-10-10	Fix several bugs pertaining to upgrades/mem leaks.	Ron Dreslinski
2006-10-09	Make memtest work with 8 memtesters	Ron Dreslinski
2006-10-09	Update the Memtester, commit a config file/test for it.	Ron Dreslinski