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path: root/tests/configs/o3-timing-checker.py
AgeCommit message (Expand)Author
2013-05-30mem: More descriptive DRAM config namesAndreas Hansson
2013-01-31mem: Add DDR3 and LPDDR2 DRAM controller configurationsAndreas Hansson
2013-01-07tests: Always specify memory mode in every test system.Ali Saidi
2012-10-30config: Unify caches used in regressions and adjust L2 MSHRsAndreas Hansson
2012-10-25config: Use SimpleDRAM in full-system, and with o3 and inorderAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-09CheckerCPU: Make some basic regression tests for CheckerCPUGeoffrey Blake