gem5 - gem5

Age	Commit message (Expand)	Author
2017-02-14	mem: Update DRAM configuration names	Wendy Elsasser
2013-06-27	config: Add a BaseSESystem builder for re-use in regressions	Andreas Hansson
2013-06-27	config: Add a system clock command-line option	Akash Bagdia
2013-05-30	mem: More descriptive DRAM config names	Andreas Hansson
2013-01-31	mem: Add DDR3 and LPDDR2 DRAM controller configurations	Andreas Hansson
2013-01-07	tests: Always specify memory mode in every test system.	Ali Saidi
2012-10-30	config: Unify caches used in regressions and adjust L2 MSHRs	Andreas Hansson
2012-10-25	config: Use SimpleDRAM in full-system, and with o3 and inorder	Andreas Hansson
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-09-25	Cache: add a response latency to the caches	Mrinmoy Ghosh
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-03-09	CheckerCPU: Make some basic regression tests for CheckerCPU	Geoffrey Blake