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path: root/tests/configs/o3-timing-mp.py
AgeCommit message (Expand)Author
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2011-12-01O3: Remove hardcoded tgts_per_mshr in O3CPU.py.Chander Sudanthi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2010-02-23cache: Make caches sharing aware and add occupancy stats.Lisa Hsu
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
2007-06-30Get rid of remaining traces of obsolete CoherenceProtocol object.Steve Reinhardt
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
2007-04-22Update configs to set the CPU clock properly.Kevin Lim
2006-10-31Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...Kevin Lim
2006-10-09Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-10-09Update configs for cpu_idRon Dreslinski
2006-10-08Clean up configs.Kevin Lim
2006-10-05First pass at snooping stuff that compiles and doesn't break.Ron Dreslinski