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o3-timing-mp.py
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Author
2012-10-25
config: Use SimpleDRAM in full-system, and with o3 and inorder
Andreas Hansson
2012-10-25
config: Use shared cache config for regressions
Andreas Hansson
2012-10-15
Mem: Use cycles to express cache-related latencies
Andreas Hansson
2012-09-25
Cache: add a response latency to the caches
Mrinmoy Ghosh
2012-05-31
Bus: Split the bus into a non-coherent and coherent bus
Andreas Hansson
2012-04-06
MEM: Enable multiple distributed generalized memories
Andreas Hansson
2012-03-02
CPU: Check that the interrupt controller is created when needed
Andreas Hansson
2012-02-13
MEM: Introduce the master/slave port roles in the Python classes
Andreas Hansson
2012-02-12
mem: fix cache stats to use request ids correctly
Dam Sunwoo
2012-01-28
SE/FS: Make SE vs. FS mode a runtime parameter.
Gabe Black
2012-01-17
MEM: Add port proxies instead of non-structural ports
Andreas Hansson
2011-12-01
O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
Chander Sudanthi
2011-03-17
Mem: Fix issue with dirty block being lost when entire block transferred to n...
Ali Saidi
2011-02-03
Config: Keep track of uncached and cached ports separately.
Gabe Black
2010-02-23
cache: Make caches sharing aware and add occupancy stats.
Lisa Hsu
2009-09-22
python: Move more code into m5.util allow SCons to use that code.
Nathan Binkert
2007-06-30
Get rid of remaining traces of obsolete CoherenceProtocol object.
Steve Reinhardt
2007-05-10
remove hit_latency and make latency do the right thing
Ali Saidi
2007-04-22
Update configs to set the CPU clock properly.
Kevin Lim
2006-10-31
Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...
Kevin Lim
2006-10-09
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-10-09
Update configs for cpu_id
Ron Dreslinski
2006-10-08
Clean up configs.
Kevin Lim
2006-10-05
First pass at snooping stuff that compiles and doesn't break.
Ron Dreslinski