summaryrefslogtreecommitdiff
path: root/tests/configs/o3-timing.py
AgeCommit message (Expand)Author
2013-01-31mem: Add DDR3 and LPDDR2 DRAM controller configurationsAndreas Hansson
2013-01-07tests: Always specify memory mode in every test system.Ali Saidi
2012-10-30config: Unify caches used in regressions and adjust L2 MSHRsAndreas Hansson
2012-10-25config: Use SimpleDRAM in full-system, and with o3 and inorderAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2011-12-01O3: Remove hardcoded tgts_per_mshr in O3CPU.py.Chander Sudanthi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
2007-04-22Update configs to set the CPU clock properly.Kevin Lim
2007-03-23A couple of minor fixes.Kevin Lim
2006-10-31Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...Kevin Lim
2006-10-08Clean up configs.Kevin Lim
2006-09-01Add o3-timing configuration for ALPHA_SE "Hello world" tests.Steve Reinhardt