gem5 - gem5

Age	Commit message (Expand)	Author
2013-01-31	mem: Add DDR3 and LPDDR2 DRAM controller configurations	Andreas Hansson
2013-01-07	tests: Always specify memory mode in every test system.	Ali Saidi
2012-10-30	config: Unify caches used in regressions and adjust L2 MSHRs	Andreas Hansson
2012-10-25	config: Use SimpleDRAM in full-system, and with o3 and inorder	Andreas Hansson
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-09-25	Cache: add a response latency to the caches	Mrinmoy Ghosh
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-03-02	CPU: Check that the interrupt controller is created when needed	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2011-12-01	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	Chander Sudanthi
2011-03-17	Mem: Fix issue with dirty block being lost when entire block transferred to n...	Ali Saidi
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
2007-05-10	remove hit_latency and make latency do the right thing	Ali Saidi
2007-04-22	Update configs to set the CPU clock properly.	Kevin Lim
2007-03-23	A couple of minor fixes.	Kevin Lim
2006-10-31	Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...	Kevin Lim
2006-10-08	Clean up configs.	Kevin Lim
2006-09-01	Add o3-timing configuration for ALPHA_SE "Hello world" tests.	Steve Reinhardt