summaryrefslogtreecommitdiff
path: root/tests/configs/pc-simple-timing-ruby.py
AgeCommit message (Expand)Author
2014-11-06ruby: interface with classic memory controllerNilay Vaish
2014-11-06ruby: single physical memory in fs modeNilay Vaish
2014-03-20config: ruby: rename _cpu_ruby_ports to _cpu_portsNilay Vaish
2014-03-20config: remove ruby_fs.pyNilay Vaish
2014-02-23ruby: route all packets through ruby portNilay Vaish
2013-08-19mem: Change AbstractMemory defaults to match the common caseAndreas Hansson
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-08-19config: Move the memory instantiation outside FSConfigAndreas Hansson
2013-07-02regressions: update a couple of configsNilay Vaish
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-05-30mem: More descriptive DRAM config namesAndreas Hansson
2013-04-22config: Add a mem-type config option to se/fs scriptsAndreas Hansson
2013-03-06ruby: remove the functional copy of memory in se modeNilay Vaish
2012-07-21Regression: Fix topologies path in failing pc-simple-timing-rubyAndreas Hansson
2012-07-10regress: ruby stat additions and config changesBrad Beckmann
2012-04-25Regression: Add a test for x86 timing full system ruby simulationNilay Vaish