gem5 - gem5

Age	Commit message (Expand)	Author
2014-11-06	ruby: interface with classic memory controller	Nilay Vaish
2014-11-06	ruby: single physical memory in fs mode	Nilay Vaish
2014-03-20	config: ruby: rename _cpu_ruby_ports to _cpu_ports	Nilay Vaish
2014-03-20	config: remove ruby_fs.py	Nilay Vaish
2014-02-23	ruby: route all packets through ruby port	Nilay Vaish
2013-08-19	mem: Change AbstractMemory defaults to match the common case	Andreas Hansson
2013-08-19	power: Add voltage domains to the clock domains	Akash Bagdia
2013-08-19	config: Move the memory instantiation outside FSConfig	Andreas Hansson
2013-07-02	regressions: update a couple of configs	Nilay Vaish
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia
2013-05-30	mem: More descriptive DRAM config names	Andreas Hansson
2013-04-22	config: Add a mem-type config option to se/fs scripts	Andreas Hansson
2013-03-06	ruby: remove the functional copy of memory in se mode	Nilay Vaish
2012-07-21	Regression: Fix topologies path in failing pc-simple-timing-ruby	Andreas Hansson
2012-07-10	regress: ruby stat additions and config changes	Brad Beckmann
2012-04-25	Regression: Add a test for x86 timing full system ruby simulation	Nilay Vaish