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path: root/tests/configs/realview-simple-timing-dual.py
AgeCommit message (Expand)Author
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
2011-08-19ARM: Add some MP regressions and clean up the disk images and kernels a bitAli Saidi