gem5 - gem5

Age	Commit message (Expand)	Author
2014-09-01	ruby: Fixes clock domains in configuration files	Emilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2014-03-20	config: ruby: rename _cpu_ruby_ports to _cpu_ports	Nilay Vaish
2013-08-20	ruby: add option for number of transitions per cycle	Nilay Vaish
2013-08-19	power: Add voltage domains to the clock domains	Akash Bagdia
2013-08-19	config: Move the memory instantiation outside FSConfig	Andreas Hansson
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia
2013-06-27	config: Add a system clock command-line option	Akash Bagdia
2013-03-06	ruby: remove the functional copy of memory in se mode	Nilay Vaish
2012-07-10	regress: ruby stat additions and config changes	Brad Beckmann
2012-04-06	regress: ruby random tester and hammer stats updates	Brad Beckmann
2012-04-06	MOESI_hammer: fixed bug with single cpu + flushes, then modified the regressi...	Brad Beckmann
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-03-28	Config: Change the way options are added	Nilay Vaish
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-01-30	Merge with main repository.	Gabe Black
2012-01-30	Ruby: Connect system port in Ruby network test	Andreas Hansson
2012-01-28	SE/FS: Make both SE and FS tests available all the time.	Gabe Black
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2011-06-30	Ruby: Add support for functional accesses	Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2011-05-23	config: tweak ruby configs to clean up hierarchy	Steve Reinhardt
2010-08-20	regress: Regression tester updates	Brad Beckmann
2010-08-17	sim: fail on implicit creation of orphans via ports	Steve Reinhardt
2010-03-21	ruby: Regression updates for new ruby config locations	Brad Beckmann
2010-01-29	m5: Regression Tester Update	Brad Beckmann