| Age | Commit message (Expand) | Author |
|---|---|---|
| 2012-05-31 | Bus: Split the bus into a non-coherent and coherent bus | Andreas Hansson |
| 2012-04-06 | MEM: Enable multiple distributed generalized memories | Andreas Hansson |
| 2012-03-02 | CPU: Check that the interrupt controller is created when needed | Andreas Hansson |
| 2012-02-13 | MEM: Introduce the master/slave port roles in the Python classes | Andreas Hansson |
| 2012-01-28 | SE/FS: Make SE vs. FS mode a runtime parameter. | Gabe Black |
| 2012-01-17 | MEM: Add port proxies instead of non-structural ports | Andreas Hansson |
| 2011-02-03 | Config: Keep track of uncached and cached ports separately. | Gabe Black |
| 2007-04-22 | Update configs to set the CPU clock properly. | Kevin Lim |
| 2006-10-31 | Remove mem parameter. Now the translating port asks the CPU's dcache's peer ... | Kevin Lim |
| 2006-10-08 | Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) | Steve Reinhardt |
| 2006-08-18 | Add caches in, fix cpu.mem param | Steve Reinhardt |
| 2006-08-16 | Finish test clean-up & reorg. | Steve Reinhardt |
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