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path: root/tests/configs/simple-timing.py
AgeCommit message (Expand)Author
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
2007-04-22Update configs to set the CPU clock properly.Kevin Lim
2006-10-31Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...Kevin Lim
2006-10-08Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)Steve Reinhardt
2006-08-21Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
2006-08-18Add caches in, fix cpu.mem paramSteve Reinhardt
2006-08-16Fix the caches not working in the regressionRon Dreslinski
2006-08-16More regression updates.Steve Reinhardt
2006-08-16Finish test clean-up & reorg.Steve Reinhardt