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path: root/tests/configs/tgen-simple-dram.py
AgeCommit message (Expand)Author
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-27config: Add a system clock command-line optionAkash Bagdia
2013-06-27config: Remove redundant explicit setting of default clocksAkash Bagdia
2013-05-30mem: More descriptive DRAM config namesAndreas Hansson
2013-01-31mem: Add DDR3 and LPDDR2 DRAM controller configurationsAndreas Hansson
2013-01-07cpu: Add support for protobuf input for the trace generatorAndreas Hansson
2012-09-21SimpleDRAM: A basic SimpleDRAM regressionAndreas Hansson