summaryrefslogtreecommitdiff
path: root/tests/configs/tgen-simple-mem.py
AgeCommit message (Expand)Author
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-05-09mem: Auto-generate CommMonitor trace file namesSascha Bischoff
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-27config: Add a system clock command-line optionAkash Bagdia
2013-06-27config: Remove redundant explicit setting of default clocksAkash Bagdia
2013-01-07cpu: Add support for protobuf input for the trace generatorAndreas Hansson
2013-01-07mem: Add tracing support in the communication monitorAndreas Hansson
2012-09-21TrafficGen: Add a basic traffic generator regressionAndreas Hansson