gem5 - gem5

Age	Commit message (Expand)	Author
2012-09-25	Cache: add a response latency to the caches	Mrinmoy Ghosh
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-03-09	cache: Allow main memory to be at disjoint address ranges.	Ali Saidi
2012-03-02	CPU: Check that the interrupt controller is created when needed	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-12	mem: fix cache stats to use request ids correctly	Dam Sunwoo
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2012-01-17	MEM: Make the bus bridge unidirectional and fixed address range	Andreas Hansson
2011-12-01	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	Chander Sudanthi
2011-03-17	Mem: Fix issue with dirty block being lost when entire block transferred to n...	Ali Saidi
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
2010-02-23	cache: Make caches sharing aware and add occupancy stats.	Lisa Hsu
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
2008-07-16	mem: use single BadAddr responder per system.	Steve Reinhardt
2008-10-20	Regression: Add single and dual boot O3 regressions. They both take about 8 m...	Ali Saidi