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path: root/tests/configs/tsunami-simple-timing-dual.py
AgeCommit message (Expand)Author
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2010-02-23cache: Make caches sharing aware and add occupancy stats.Lisa Hsu
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
2008-07-16mem: use single BadAddr responder per system.Steve Reinhardt
2007-08-10Regression: Add an I/O Cache to the full system regressions that have a cache.Ali Saidi
2007-06-30Get rid of remaining traces of obsolete CoherenceProtocol object.Steve Reinhardt
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
2006-10-31Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...Kevin Lim
2006-10-17Enable MP systems via cmd-line flag in fs.py.Steve Reinhardt
2006-10-08Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)Steve Reinhardt
2006-08-18Add caches in, fix cpu.mem paramSteve Reinhardt
2006-08-16Finish test clean-up & reorg.Steve Reinhardt