gem5 - gem5

Age	Commit message (Expand)	Author
2013-08-19	power: Add voltage domains to the clock domains	Akash Bagdia
2013-08-19	config: Move the memory instantiation outside FSConfig	Andreas Hansson
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia
2013-06-27	config: Add a system clock command-line option	Akash Bagdia
2013-05-30	mem: More descriptive DRAM config names	Andreas Hansson
2013-04-22	config: Add a mem-type config option to se/fs scripts	Andreas Hansson
2013-01-07	config: Do not use hardcoded physmem in fs script	Andreas Hansson
2012-09-24	Regression: Set the clock for twosys-tsunami CPUs	Andreas Hansson
2012-08-22	Bridge: Remove NACKs in the bridge and unify with packet queue	Andreas Hansson
2012-03-02	CPU: Check that the interrupt controller is created when needed	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2012-01-17	MEM: Make the bus bridge unidirectional and fixed address range	Andreas Hansson
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
2006-12-01	change this to be a quick one so that it's in the regressions every night - i...	Lisa Hsu
2006-12-01	add a simple netperf-stream test to the long tests.	Lisa Hsu