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AgeCommit message (Expand)Author
2013-05-30mem: More descriptive DRAM config namesAndreas Hansson
2013-04-28config: Added memory type to t1000 regressionAndreas Hansson
2013-04-23x86: regressions: add switcher full testNilay Vaish
2013-04-22config: Add a mem-type config option to se/fs scriptsAndreas Hansson
2013-04-22tests: Add support for testing KVM-based CPUsAndreas Sandberg
2013-04-22arm: Enable support for triggering a sim panic on kernel panicsAndreas Sandberg
2013-03-06ruby: remove the functional copy of memory in se modeNilay Vaish
2013-02-15config: Move CPU handover logic to m5.switchCpus()Andreas Sandberg
2013-01-31mem: Add DDR3 and LPDDR2 DRAM controller configurationsAndreas Hansson
2013-01-07tests: Add CPU switching testsAndreas Sandberg
2013-01-07config: Do not use hardcoded physmem in fs scriptAndreas Hansson
2013-01-07cpu: Add support for protobuf input for the trace generatorAndreas Hansson
2013-01-07mem: Add tracing support in the communication monitorAndreas Hansson
2013-01-07tests: Always specify memory mode in every test system.Ali Saidi
2013-01-07tests: Create base classes to encapsulate common test configurationsAndreas Sandberg
2012-10-31stats: Update stats for fixed simple-atomic-mp configAndreas Hansson
2012-10-31config: Fix a typo in the simple-atomic-mp configurationAndreas Hansson
2012-10-30config: Unify caches used in regressions and adjust L2 MSHRsAndreas Hansson
2012-10-26config: Fix the cache class naming in regression scriptsAndreas Hansson
2012-10-25config: Use SimpleDRAM in full-system, and with o3 and inorderAndreas Hansson
2012-10-25config: Use shared cache config for regressionsAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-10-15Configs: Set the memtest clock to a reasonable valueAndreas Hansson
2012-10-15Regression: Use addTwoLevelCacheHierarchy in configsAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-24Regression: Set the clock for twosys-tsunami CPUsAndreas Hansson
2012-09-21SimpleDRAM: A basic SimpleDRAM regressionAndreas Hansson
2012-09-21TrafficGen: Add a basic traffic generator regressionAndreas Hansson
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
2012-07-21Regression: Fix topologies path in failing pc-simple-timing-rubyAndreas Hansson
2012-07-12Mem: Make SimpleMemory single portedAndreas Hansson
2012-07-10regress: ruby stat additions and config changesBrad Beckmann
2012-06-11Regression: Fix some bugs in simple-timing-mp-ruby.py.Marc Orr
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-04-25Regression: Add a test for x86 timing full system ruby simulationNilay Vaish
2012-04-06regress: ruby random tester and hammer stats updatesBrad Beckmann
2012-04-06MOESI_hammer: fixed bug with single cpu + flushes, then modified the regressi...Brad Beckmann
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-28Config: Change the way options are addedNilay Vaish
2012-03-09CheckerCPU: Make some basic regression tests for CheckerCPUGeoffrey Blake
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-08Fix the SPARC fs regression by adding a call to createInterruptController.Gabe Black
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
2012-02-14Script: Fix the scripts that use the num_cpus cache parameterAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
2012-01-30Merge with main repository.Gabe Black
2012-01-30Ruby: Connect system port in Ruby network testAndreas Hansson
2012-01-28SE/FS: Make both SE and FS tests available all the time.Gabe Black
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
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