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AgeCommit message (Expand)Author
2015-07-07sim: Decouple draining from the SimObject hierarchyAndreas Sandberg
2015-07-07tests: Skip SPARC tests if the required binaries are missingAndreas Sandberg
2015-07-03mem: Allow read-only caches and check complianceAndreas Hansson
2015-03-19test, arm: Add scripts to test checkpointsAndreas Sandberg
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
2015-02-11cpu: Tidy up the MemTest and make false sharing more obviousAndreas Hansson
2015-01-20tests: Remove deprecated InOrderCPU testsAndreas Hansson
2014-12-23tests: Add a regression for the stack distance calculatorAndreas Hansson
2014-11-06ruby: interface with classic memory controllerNilay Vaish
2014-11-06ruby: single physical memory in fs modeNilay Vaish
2014-10-29arm, tests: Update config files to more recent kernels and create 64-bit regr...Ali Saidi
2014-09-20tests: Use more representative configs for ARM testsAndreas Hansson
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-09-20tests: Add a memtest version using the ideal SnoopFilterAndreas Hansson
2014-09-03alpha: Stop using 'inorder' and rely entirely on 'minor'Andreas Hansson
2014-09-03tests: Use O3_ARM_v7a config for full-system ARM regressionsAndreas Hansson
2014-09-01ruby: Fixes clock domains in configuration filesEmilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2014-07-23cpu: Minor CPU add regression tests for ARM and ALPHAAndrew Bardsley
2014-05-09tests: Reflect name change in DRAM testsAndreas Hansson
2014-05-09mem: Auto-generate CommMonitor trace file namesSascha Bischoff
2014-03-20config: ruby: rename _cpu_ruby_ports to _cpu_portsNilay Vaish
2014-03-20config: remove ruby_fs.pyNilay Vaish
2014-03-20ruby: no piobus in se modeNilay Vaish
2014-02-24ruby: correct errors in changeset 4eec7bdde5b0Nilay Vaish
2014-02-23ruby: route all packets through ruby portNilay Vaish
2014-01-03config, x86: move kernel specification from tests to FSConfig.pySteve Reinhardt
2013-11-14tests: suppress output on switcheroo testsSteve Reinhardt
2013-11-01test: Use SimpleMemory for atomic full-system testsAndreas Hansson
2013-08-20ruby: add option for number of transitions per cycleNilay Vaish
2013-08-19mem: Change AbstractMemory defaults to match the common caseAndreas Hansson
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-08-19config: Move the memory instantiation outside FSConfigAndreas Hansson
2013-07-02regressions: update a couple of configsNilay Vaish
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-27config: Add a BaseSESystem builder for re-use in regressionsAndreas Hansson
2013-06-27config: Add a system clock command-line optionAkash Bagdia
2013-06-27config: Remove redundant explicit setting of default clocksAkash Bagdia
2013-05-30mem: More descriptive DRAM config namesAndreas Hansson
2013-04-28config: Added memory type to t1000 regressionAndreas Hansson
2013-04-23x86: regressions: add switcher full testNilay Vaish
2013-04-22config: Add a mem-type config option to se/fs scriptsAndreas Hansson
2013-04-22tests: Add support for testing KVM-based CPUsAndreas Sandberg
2013-04-22arm: Enable support for triggering a sim panic on kernel panicsAndreas Sandberg
2013-03-06ruby: remove the functional copy of memory in se modeNilay Vaish
2013-02-15config: Move CPU handover logic to m5.switchCpus()Andreas Sandberg
2013-01-31mem: Add DDR3 and LPDDR2 DRAM controller configurationsAndreas Hansson
2013-01-07tests: Add CPU switching testsAndreas Sandberg
2013-01-07config: Do not use hardcoded physmem in fs scriptAndreas Hansson
2013-01-07cpu: Add support for protobuf input for the trace generatorAndreas Hansson
2013-01-07mem: Add tracing support in the communication monitorAndreas Hansson