gem5 - gem5

Age	Commit message (Expand)	Author
2015-07-07	sim: Decouple draining from the SimObject hierarchy	Andreas Sandberg
2015-07-07	tests: Skip SPARC tests if the required binaries are missing	Andreas Sandberg
2015-07-03	mem: Allow read-only caches and check compliance	Andreas Hansson
2015-03-19	test, arm: Add scripts to test checkpoints	Andreas Sandberg
2015-03-02	mem: Move crossbar default latencies to subclasses	Andreas Hansson
2015-02-11	cpu: Tidy up the MemTest and make false sharing more obvious	Andreas Hansson
2015-01-20	tests: Remove deprecated InOrderCPU tests	Andreas Hansson
2014-12-23	tests: Add a regression for the stack distance calculator	Andreas Hansson
2014-11-06	ruby: interface with classic memory controller	Nilay Vaish
2014-11-06	ruby: single physical memory in fs mode	Nilay Vaish
2014-10-29	arm, tests: Update config files to more recent kernels and create 64-bit regr...	Ali Saidi
2014-09-20	tests: Use more representative configs for ARM tests	Andreas Hansson
2014-09-20	mem: Rename Bus to XBar to better reflect its behaviour	Andreas Hansson
2014-09-20	tests: Add a memtest version using the ideal SnoopFilter	Andreas Hansson
2014-09-03	alpha: Stop using 'inorder' and rely entirely on 'minor'	Andreas Hansson
2014-09-03	tests: Use O3_ARM_v7a config for full-system ARM regressions	Andreas Hansson
2014-09-01	ruby: Fixes clock domains in configuration files	Emilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2014-07-23	cpu: Minor CPU add regression tests for ARM and ALPHA	Andrew Bardsley
2014-05-09	tests: Reflect name change in DRAM tests	Andreas Hansson
2014-05-09	mem: Auto-generate CommMonitor trace file names	Sascha Bischoff
2014-03-20	config: ruby: rename _cpu_ruby_ports to _cpu_ports	Nilay Vaish
2014-03-20	config: remove ruby_fs.py	Nilay Vaish
2014-03-20	ruby: no piobus in se mode	Nilay Vaish
2014-02-24	ruby: correct errors in changeset 4eec7bdde5b0	Nilay Vaish
2014-02-23	ruby: route all packets through ruby port	Nilay Vaish
2014-01-03	config, x86: move kernel specification from tests to FSConfig.py	Steve Reinhardt
2013-11-14	tests: suppress output on switcheroo tests	Steve Reinhardt
2013-11-01	test: Use SimpleMemory for atomic full-system tests	Andreas Hansson
2013-08-20	ruby: add option for number of transitions per cycle	Nilay Vaish
2013-08-19	mem: Change AbstractMemory defaults to match the common case	Andreas Hansson
2013-08-19	power: Add voltage domains to the clock domains	Akash Bagdia
2013-08-19	config: Move the memory instantiation outside FSConfig	Andreas Hansson
2013-07-02	regressions: update a couple of configs	Nilay Vaish
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia
2013-06-27	config: Add a BaseSESystem builder for re-use in regressions	Andreas Hansson
2013-06-27	config: Add a system clock command-line option	Akash Bagdia
2013-06-27	config: Remove redundant explicit setting of default clocks	Akash Bagdia
2013-05-30	mem: More descriptive DRAM config names	Andreas Hansson
2013-04-28	config: Added memory type to t1000 regression	Andreas Hansson
2013-04-23	x86: regressions: add switcher full test	Nilay Vaish
2013-04-22	config: Add a mem-type config option to se/fs scripts	Andreas Hansson
2013-04-22	tests: Add support for testing KVM-based CPUs	Andreas Sandberg
2013-04-22	arm: Enable support for triggering a sim panic on kernel panics	Andreas Sandberg
2013-03-06	ruby: remove the functional copy of memory in se mode	Nilay Vaish
2013-02-15	config: Move CPU handover logic to m5.switchCpus()	Andreas Sandberg
2013-01-31	mem: Add DDR3 and LPDDR2 DRAM controller configurations	Andreas Hansson
2013-01-07	tests: Add CPU switching tests	Andreas Sandberg
2013-01-07	config: Do not use hardcoded physmem in fs script	Andreas Hansson
2013-01-07	cpu: Add support for protobuf input for the trace generator	Andreas Hansson
2013-01-07	mem: Add tracing support in the communication monitor	Andreas Hansson