gem5 - gem5

Age	Commit message (Expand)	Author
2013-02-15	config: Move CPU handover logic to m5.switchCpus()	Andreas Sandberg
2013-01-31	mem: Add DDR3 and LPDDR2 DRAM controller configurations	Andreas Hansson
2013-01-07	tests: Add CPU switching tests	Andreas Sandberg
2013-01-07	config: Do not use hardcoded physmem in fs script	Andreas Hansson
2013-01-07	cpu: Add support for protobuf input for the trace generator	Andreas Hansson
2013-01-07	mem: Add tracing support in the communication monitor	Andreas Hansson
2013-01-07	tests: Always specify memory mode in every test system.	Ali Saidi
2013-01-07	tests: Create base classes to encapsulate common test configurations	Andreas Sandberg
2012-10-31	stats: Update stats for fixed simple-atomic-mp config	Andreas Hansson
2012-10-31	config: Fix a typo in the simple-atomic-mp configuration	Andreas Hansson
2012-10-30	config: Unify caches used in regressions and adjust L2 MSHRs	Andreas Hansson
2012-10-26	config: Fix the cache class naming in regression scripts	Andreas Hansson
2012-10-25	config: Use SimpleDRAM in full-system, and with o3 and inorder	Andreas Hansson
2012-10-25	config: Use shared cache config for regressions	Andreas Hansson
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-10-15	Configs: Set the memtest clock to a reasonable value	Andreas Hansson
2012-10-15	Regression: Use addTwoLevelCacheHierarchy in configs	Andreas Hansson
2012-09-25	Cache: add a response latency to the caches	Mrinmoy Ghosh
2012-09-24	Regression: Set the clock for twosys-tsunami CPUs	Andreas Hansson
2012-09-21	SimpleDRAM: A basic SimpleDRAM regression	Andreas Hansson
2012-09-21	TrafficGen: Add a basic traffic generator regression	Andreas Hansson
2012-08-22	Bridge: Remove NACKs in the bridge and unify with packet queue	Andreas Hansson
2012-07-21	Regression: Fix topologies path in failing pc-simple-timing-ruby	Andreas Hansson
2012-07-12	Mem: Make SimpleMemory single ported	Andreas Hansson
2012-07-10	regress: ruby stat additions and config changes	Brad Beckmann
2012-06-11	Regression: Fix some bugs in simple-timing-mp-ruby.py.	Marc Orr
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-04-25	Regression: Add a test for x86 timing full system ruby simulation	Nilay Vaish
2012-04-06	regress: ruby random tester and hammer stats updates	Brad Beckmann
2012-04-06	MOESI_hammer: fixed bug with single cpu + flushes, then modified the regressi...	Brad Beckmann
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-03-28	Config: Change the way options are added	Nilay Vaish
2012-03-09	CheckerCPU: Make some basic regression tests for CheckerCPU	Geoffrey Blake
2012-03-09	cache: Allow main memory to be at disjoint address ranges.	Ali Saidi
2012-03-08	Fix the SPARC fs regression by adding a call to createInterruptController.	Gabe Black
2012-03-02	CPU: Check that the interrupt controller is created when needed	Andreas Hansson
2012-02-14	Script: Fix the scripts that use the num_cpus cache parameter	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-12	mem: fix cache stats to use request ids correctly	Dam Sunwoo
2012-01-30	Merge with main repository.	Gabe Black
2012-01-30	Ruby: Connect system port in Ruby network test	Andreas Hansson
2012-01-28	SE/FS: Make both SE and FS tests available all the time.	Gabe Black
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-17	MEM: Make the bus bridge unidirectional and fixed address range	Andreas Hansson
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2012-01-07	Merge with the main repository again.	Gabe Black
2011-12-01	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	Chander Sudanthi
2011-10-08	Configs: Use connectAllPorts to connect ports for simple-timing-ruby.	Gabe Black
2011-08-19	ARM: Add some MP regressions and clean up the disk images and kernels a bit	Ali Saidi