index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
tests
/
configs
Age
Commit message (
Expand
)
Author
2013-08-19
mem: Change AbstractMemory defaults to match the common case
Andreas Hansson
2013-08-19
power: Add voltage domains to the clock domains
Akash Bagdia
2013-08-19
config: Move the memory instantiation outside FSConfig
Andreas Hansson
2013-07-02
regressions: update a couple of configs
Nilay Vaish
2013-06-27
sim: Add the notion of clock domains to all ClockedObjects
Akash Bagdia
2013-06-27
config: Add a BaseSESystem builder for re-use in regressions
Andreas Hansson
2013-06-27
config: Add a system clock command-line option
Akash Bagdia
2013-06-27
config: Remove redundant explicit setting of default clocks
Akash Bagdia
2013-05-30
mem: More descriptive DRAM config names
Andreas Hansson
2013-04-28
config: Added memory type to t1000 regression
Andreas Hansson
2013-04-23
x86: regressions: add switcher full test
Nilay Vaish
2013-04-22
config: Add a mem-type config option to se/fs scripts
Andreas Hansson
2013-04-22
tests: Add support for testing KVM-based CPUs
Andreas Sandberg
2013-04-22
arm: Enable support for triggering a sim panic on kernel panics
Andreas Sandberg
2013-03-06
ruby: remove the functional copy of memory in se mode
Nilay Vaish
2013-02-15
config: Move CPU handover logic to m5.switchCpus()
Andreas Sandberg
2013-01-31
mem: Add DDR3 and LPDDR2 DRAM controller configurations
Andreas Hansson
2013-01-07
tests: Add CPU switching tests
Andreas Sandberg
2013-01-07
config: Do not use hardcoded physmem in fs script
Andreas Hansson
2013-01-07
cpu: Add support for protobuf input for the trace generator
Andreas Hansson
2013-01-07
mem: Add tracing support in the communication monitor
Andreas Hansson
2013-01-07
tests: Always specify memory mode in every test system.
Ali Saidi
2013-01-07
tests: Create base classes to encapsulate common test configurations
Andreas Sandberg
2012-10-31
stats: Update stats for fixed simple-atomic-mp config
Andreas Hansson
2012-10-31
config: Fix a typo in the simple-atomic-mp configuration
Andreas Hansson
2012-10-30
config: Unify caches used in regressions and adjust L2 MSHRs
Andreas Hansson
2012-10-26
config: Fix the cache class naming in regression scripts
Andreas Hansson
2012-10-25
config: Use SimpleDRAM in full-system, and with o3 and inorder
Andreas Hansson
2012-10-25
config: Use shared cache config for regressions
Andreas Hansson
2012-10-15
Mem: Use cycles to express cache-related latencies
Andreas Hansson
2012-10-15
Configs: Set the memtest clock to a reasonable value
Andreas Hansson
2012-10-15
Regression: Use addTwoLevelCacheHierarchy in configs
Andreas Hansson
2012-09-25
Cache: add a response latency to the caches
Mrinmoy Ghosh
2012-09-24
Regression: Set the clock for twosys-tsunami CPUs
Andreas Hansson
2012-09-21
SimpleDRAM: A basic SimpleDRAM regression
Andreas Hansson
2012-09-21
TrafficGen: Add a basic traffic generator regression
Andreas Hansson
2012-08-22
Bridge: Remove NACKs in the bridge and unify with packet queue
Andreas Hansson
2012-07-21
Regression: Fix topologies path in failing pc-simple-timing-ruby
Andreas Hansson
2012-07-12
Mem: Make SimpleMemory single ported
Andreas Hansson
2012-07-10
regress: ruby stat additions and config changes
Brad Beckmann
2012-06-11
Regression: Fix some bugs in simple-timing-mp-ruby.py.
Marc Orr
2012-05-31
Bus: Split the bus into a non-coherent and coherent bus
Andreas Hansson
2012-04-25
Regression: Add a test for x86 timing full system ruby simulation
Nilay Vaish
2012-04-06
regress: ruby random tester and hammer stats updates
Brad Beckmann
2012-04-06
MOESI_hammer: fixed bug with single cpu + flushes, then modified the regressi...
Brad Beckmann
2012-04-06
MEM: Enable multiple distributed generalized memories
Andreas Hansson
2012-03-28
Config: Change the way options are added
Nilay Vaish
2012-03-09
CheckerCPU: Make some basic regression tests for CheckerCPU
Geoffrey Blake
2012-03-09
cache: Allow main memory to be at disjoint address ranges.
Ali Saidi
2012-03-08
Fix the SPARC fs regression by adding a call to createInterruptController.
Gabe Black
[next]