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regressions need to access this file to setup the InOrderCPU object
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Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
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minutes to complete.
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--HG--
extra : convert_revision : 8ba96e21be2f602eed8258d410038dbe998ef176
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--HG--
extra : convert_revision : c5555b00bef1b304a84886188ad2c0dcb4d7c5b9
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configs/example/memtest.py:
PhysicalMemory has vector of uniform ports instead of one special one.
Other updates to fix obsolete brokenness.
src/mem/physical.cc:
src/mem/physical.hh:
src/python/m5/objects/PhysicalMemory.py:
Have vector of uniform ports instead of one special one.
src/python/swig/pyobject.cc:
Add comment.
--HG--
extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1
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set the latency parameter in terms of a latency
add caches to tsunami-simple configs
configs/common/Caches.py:
tests/configs/memtest.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
set the latency parameter in terms of a latency
configs/common/FSConfig.py:
give the bridge a default latency too
src/mem/cache/cache_builder.cc:
src/python/m5/objects/BaseCache.py:
remove hit_latency and make latency do the right thing
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
add caches to tsunami-simple configs
--HG--
extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1
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--HG--
extra : convert_revision : 62fec666f987e9a9a441e319458908483cd2c5ff
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2
src/cpu/base_dyn_inst.hh:
Hand merge. Line is no longer needed because it's handled in the ISA.
--HG--
extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
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1. Set CPU ID in all modes for the O3 CPU.
2. Use nextCycle() function to prevent phase drift in O3 CPU.
3. Remove assertion in rename map that is no longer true.
src/cpu/o3/alpha/cpu_builder.cc:
Allow for CPU id in all modes, not just full system. Also include a parameter that was left out by accident.
src/cpu/o3/alpha/cpu_impl.hh:
Set the CPU ID properly.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
Use nextCycle() function so that the CPU does not get out of phase when starting up from quiesces.
src/cpu/o3/rename_map.cc:
Remove assertion that is no longer true.
tests/configs/o3-timing.py:
Set CPU's id to 0.
--HG--
extra : convert_revision : 2b69c19adfce2adcc2d1939e89d702bd6674d5d5
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directly configured by python. Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.
--HG--
extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
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src/dev/sparc/iob.cc:
don't warn on cpu restart/idle/halt stuff
tests/SConscript:
add sparc target in test Sconscript
util/regress:
Add SPARC_FS target in regress
--HG--
extra : convert_revision : 37fa21700ec4c350d87ca9723bc3359feb81c50a
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Caveats:
- Even though memtest is ISA-independent, it will only
run for the Alpha builds, since there's no way to specify
ISA-independent reference files and I didn't want to commit
3 copies since I'm not sure we want to run it for all the
different ISAs anyway.
- Reference outputs were generated on my laptop,
so performance numbers will be low compared to zizzer.
--HG--
extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
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it's only maybe 15 min. long.
tests/configs/twosys-tsunami-simple-atomic.py:
don't need this import
--HG--
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
rename : tests/long/80.netperf-stream/test.py => tests/quick/80.netperf-stream/test.py
extra : convert_revision : 68497b2ef8b21590cb6c636485703e46dc616513
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tests/SConscript:
add a new configuration for two-system tests (atomic simple only)
--HG--
extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
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for its MemObject instead of having to have a paramter for the MemObject.
configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
No need for mem parameter any more.
src/cpu/checker/cpu.cc:
Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
Remove memory parameter.
--HG--
extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
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I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Fix corner case on assertion
tests/configs/memtest.py:
Updated memtester with uncacheable addresses and functional accesses
--HG--
extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
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configs/example/fs.py:
Add flag for MP server systems.
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/IntrControl.py:
Change CPU from 'any' to 'cpu[0]' to work better with MP sytems.
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-timing-dual.py:
Don't need to set console & intrcontrol cpu
params anymore (default is fixed now).
--HG--
extra : convert_revision : 9417b12b1b395ff7d6a9f2894e4123923c754daf
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Get over 500,000 reads on each of 8 testers before memory leak becomes large.
tests/configs/memtest.py:
Update test to be more interesting
--HG--
extra : convert_revision : 4258b798fbeeed2a376f1bfac100a109eb05620e
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision : 87f83c4edf6ea51adc767d98265d1e74c0fbb46f
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src/mem/cache/base_cache.cc:
Fix a bug about not having a request to send
src/mem/cache/base_cache.hh:
Fix a bug with the blocking code
src/mem/cache/cache.hh:
AFix a bug with snoop hits in WB buffer
src/mem/cache/cache_impl.hh:
Fix a bug with snoop hits in WB buffer
Also, add better DPRINTF's
src/mem/cache/miss/miss_queue.cc:
Fix a bug with upgrades (Need to clean it up later)
src/mem/cache/miss/mshr.cc:
Fix a memory leak bug, still some outstanding with writebacks not being deleted
src/mem/cache/miss/mshr_queue.cc:
Fix a bug about upgrades (need to clean up later)
src/mem/packet.hh:
Fix for newly added cmd attribute for upgrades
tests/configs/memtest.py:
More interesting testcase
--HG--
extra : convert_revision : fcb4f17dd58b537bb4f67a8c835f50e455e8c688
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
Hand merge.
--HG--
extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
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tests/configs/o3-timing-mp.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
Update config for cpu_id
--HG--
extra : convert_revision : 32a1971997920473164ba12f2b121cb640bad7ac
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src/mem/physical.cc:
Update comment to match memtest use
src/python/m5/objects/PhysicalMemory.py:
Make memtester have a way to connect functionally
tests/configs/memtest.py:
Properly create 8 memtesters and connect them to the memory system
--HG--
extra : convert_revision : e5a2dd9c8918d58051b553b5c6a14785d48b34ca
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src/cpu/SConscript:
Add memtester to the compilation environment.
Someone who knows this better should make the MemTest a cpu model parameter.
For now attached with the build of o3 cpu.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
Update Memtest for new mem system
src/python/m5/objects/MemTest.py:
Update memtest python description
--HG--
extra : convert_revision : d6a63e08fda0975a7abfb23814a86a0caf53e482
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and PhysicalMemory. *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.
src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
--HG--
extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
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configs/common/FSConfig.py:
configs/common/SysPaths.py:
configs/example/fs.py:
configs/example/se.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
Clean up configs by removing FullO3Config and instead using default values.
src/python/m5/objects/FUPool.py:
Add in default FUPool.
src/python/m5/objects/O3CPU.py:
Use defaults better. Also set checker parameters, and fix up a config bug.
--HG--
extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b
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And small other tweaks to snooping coherence.
src/mem/cache/base_cache.hh:
Make timing response at the time of send.
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
Update probe interface to be bi-directional for functional accesses
src/mem/packet.hh:
Add the function to create an atomic response to a given request
--HG--
extra : convert_revision : 04075a117cf30a7df16e6d3ce485543cc77d4ca6
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Still need:
-Handle NACK's on the recieve side
-Distinguish top level caches
-Handle repsonses from caches failing the fast path
-Handle BusError and propogate it
-Fix the invalidate packet associated with snooping in the cache
src/mem/bus.cc:
Make sure to snoop on functional accesses
src/mem/cache/base_cache.cc:
Wait to make a request into a response until it is ready to be issued
src/mem/cache/base_cache.hh:
Support range changes for snoops
Set up snoop responses for cache->cache transfers
src/mem/cache/cache_impl.hh:
Only access the cache if it wasn't satisfied by cache->cache transfer
Handle snoop phases (detect block, then snoop)
Fix functional access to work properly (still need to fix snoop path for functional accesses)
--HG--
extra : convert_revision : 4c25f11d7a996c1f56f4f7b55dde87a344e5fdf8
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build_opts/ALPHA_SE:
Add O3CPU to default CPU model list.
tests/SConscript:
Add o3-timing configuration.
--HG--
extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
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into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem
src/python/m5/objects/BaseCPU.py:
Merge duplicate change
--HG--
extra : convert_revision : 214e57999ee78aadfc86e1f0b7198ff0d981ce16
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--HG--
extra : convert_revision : 486283d83786807c72bb4601e4b9613b55d8802c
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src/python/m5/objects/BaseCPU.py:
Make mem parameter a MemObject, not just a PhysicalMemory
Fix a reference not using self
tests/configs/simple-atomic.py:
Set the mem paramter
tests/configs/simple-timing.py:
Set the mem parameter
--HG--
extra : convert_revision : 6bd9df36831a1c5bafc9e88ab945c2ebe91db785
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Get rid of caches in simple-timing config for now.
tests/SConscript:
another line for diff to ignore
tests/configs/simple-timing.py:
turn off caches for now
tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout:
update for inst/tick rate (old one was debug?)
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout:
works now (no caches)
--HG--
extra : convert_revision : 472030f63297346976db6274a78235c93d4eef8e
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configs/common/FSConfig.py:
Add default Machine() param
configs/example/fs.py:
configs/example/se.py:
make it work again
src/python/m5/objects/BaseCPU.py:
Make mem PhysicalMemory so that a Parent.any proxy works well
src/sim/process.cc:
Increase default stack size so we don't get an
'increasing stack' message on 'hello world'
tests/SConscript:
Add full list of current configs.
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
don't need SEConfig anymore
tests/quick/00.hello/test.py:
tests/quick/20.eio-short/test.py:
fix
tests/run.py:
move configs to separate dir
--HG--
rename : configs/test/fs.py => configs/example/fs.py
rename : configs/test/test.py => configs/example/se.py
rename : tests/simple-atomic.py => tests/configs/simple-atomic.py
rename : tests/simple-timing.py => tests/configs/simple-timing.py
rename : tests/linux-mpboot/ref/alpha/atomic/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
rename : tests/linux-mpboot/ref/alpha/atomic/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out
rename : tests/linux-mpboot/ref/alpha/atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
rename : tests/linux-mpboot/ref/alpha/atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
rename : tests/linux-mpboot/ref/alpha/atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
rename : tests/linux-mpboot/ref/alpha/atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
rename : tests/linux-boot/ref/alpha/atomic/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
rename : tests/linux-boot/ref/alpha/atomic/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out
rename : tests/linux-boot/ref/alpha/atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
rename : tests/linux-boot/ref/alpha/atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
rename : tests/linux-boot/ref/alpha/atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
rename : tests/linux-boot/ref/alpha/atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
rename : tests/linux-mpboot/ref/alpha/timing/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
rename : tests/linux-mpboot/ref/alpha/timing/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out
rename : tests/linux-mpboot/ref/alpha/timing/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
rename : tests/linux-mpboot/ref/alpha/timing/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
rename : tests/linux-mpboot/ref/alpha/timing/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
rename : tests/linux-mpboot/ref/alpha/timing/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
rename : tests/test-progs/hello/bin/mips/linux/hello_mips => tests/test-progs/hello/bin/mips/linux/hello
rename : tests/test-progs/hello/bin/sparc/bin => tests/test-progs/hello/bin/sparc/linux/hello
extra : convert_revision : d68ee6d7eefa7ba57370f3fb3c3589f86a6ea6b4
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