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AgeCommit message (Expand)Author
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-10-15Configs: Set the memtest clock to a reasonable valueAndreas Hansson
2012-10-15Regression: Use addTwoLevelCacheHierarchy in configsAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-24Regression: Set the clock for twosys-tsunami CPUsAndreas Hansson
2012-09-21SimpleDRAM: A basic SimpleDRAM regressionAndreas Hansson
2012-09-21TrafficGen: Add a basic traffic generator regressionAndreas Hansson
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
2012-07-21Regression: Fix topologies path in failing pc-simple-timing-rubyAndreas Hansson
2012-07-12Mem: Make SimpleMemory single portedAndreas Hansson
2012-07-10regress: ruby stat additions and config changesBrad Beckmann
2012-06-11Regression: Fix some bugs in simple-timing-mp-ruby.py.Marc Orr
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-04-25Regression: Add a test for x86 timing full system ruby simulationNilay Vaish
2012-04-06regress: ruby random tester and hammer stats updatesBrad Beckmann
2012-04-06MOESI_hammer: fixed bug with single cpu + flushes, then modified the regressi...Brad Beckmann
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-28Config: Change the way options are addedNilay Vaish
2012-03-09CheckerCPU: Make some basic regression tests for CheckerCPUGeoffrey Blake
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-08Fix the SPARC fs regression by adding a call to createInterruptController.Gabe Black
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
2012-02-14Script: Fix the scripts that use the num_cpus cache parameterAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
2012-01-30Merge with main repository.Gabe Black
2012-01-30Ruby: Connect system port in Ruby network testAndreas Hansson
2012-01-28SE/FS: Make both SE and FS tests available all the time.Gabe Black
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2012-01-28Merge with the main repo.Gabe Black
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2012-01-07Merge with the main repository again.Gabe Black
2011-12-01O3: Remove hardcoded tgts_per_mshr in O3CPU.py.Chander Sudanthi
2011-10-08Configs: Use connectAllPorts to connect ports for simple-timing-ruby.Gabe Black
2011-08-19ARM: Add some MP regressions and clean up the disk images and kernels a bitAli Saidi
2011-07-05X86: Add a config for an FS regression on O3.Gabe Black
2011-06-30Ruby: Add support for functional accessesBrad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2011-06-19inorder: make InOrder CPU FS compilable/visibleKorey Sewell
2011-05-23config: tweak ruby configs to clean up hierarchySteve Reinhardt
2011-03-17ARM: Update stats for the previous changes and add ARM_FS/O3 regression.Ali Saidi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-02-23ARM: Clarifies creation of Linux and baremetal ARM systems.Ali Saidi
2011-02-08memtest: due to contention increase, increased deadlock thresholdBrad Beckmann
2011-02-07X86: Add scripts to support X86 FS configurations in the regressions.Gabe Black
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2010-11-08ARM: Add full-system regressionsAli Saidi
2010-08-20regress: Regression tester updatesBrad Beckmann
2010-08-17sim: fail on implicit creation of orphans via portsSteve Reinhardt
2010-03-21ruby: Regression updates for new ruby config locationsBrad Beckmann