gem5 - gem5

Age	Commit message (Collapse)	Author
2011-08-19	O3: Update stats for LSQ changes.	Ali Saidi

2011-07-10	O3: Update stats for fetch and bp changes.	Ali Saidi

2011-05-23	Stats: Update stats for minor O3 changes below.	Ali Saidi

2011-05-13	ARM: Fix up stats for previous changes to condition codes	Ali Saidi

2011-04-22	tests: updates for stat name change	Nathan Binkert

2011-04-19	tests: update stats for name changes	Nathan Binkert

2011-04-12	ARM: Fix stats for ARM_SE checkpoint restore fix.	Ali Saidi
	Register reads/writes done in startup() count against the stats while they don't count if done in initState().
2011-04-04	ARM: Update stats for previous changes.	Ali Saidi

2011-04-04	O3: Update stats for memory order violation checking patch.	Ali Saidi

2011-03-17	ARM: Update stats for the previous changes and add ARM_FS/O3 regression.	Ali Saidi

2011-03-17	Stats: Update the statistics for rfe patch.	Ali Saidi

2011-02-23	ARM: Update regression tests for preceeding changes.	Ali Saidi

2011-02-07	Stats: Re update stats.	Gabe Black

2011-01-18	ARM/O3: Add regressions for ARM w/ O3 CPU.	Ali Saidi

2010-11-08	ARM: Update SE stats for TLB stats additions	Ali Saidi

2010-11-08	ARM: Add full-system regressions	Ali Saidi

2010-09-21	stats: update stats for previous cset	Steve Reinhardt
	Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
2010-09-09	stats: update stats for preceding coherence changes	Steve Reinhardt
	Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-08-25	ARM: Update regression tests for ldr/str microcode changes.	Ali Saidi

2010-08-17	tests: update reference config.ini files for previous cset	Steve Reinhardt
	Rename 'responder_set' to 'use_default_range'.
2010-07-27	ARM: Add regression tests	Ali Saidi