gem5 - gem5

Age	Commit message (Collapse)	Author
2011-07-10	O3: Update stats for fetch and bp changes.	Ali Saidi

2011-07-02	Stats: Update stats for the x86 store fault fix.	Gabe Black

2011-06-20	alpha:o3:simple: update simout/err files	Korey Sewell
	A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-19	inorder: update SE regressions	Korey Sewell

2011-06-12	sparc: update long regressions	Korey Sewell

2011-05-23	Stats: Update stats for minor O3 changes below.	Ali Saidi

2011-05-13	ARM: Fix up stats for previous changes to condition codes	Ali Saidi

2011-04-22	tests: updates for stat name change	Nathan Binkert

2011-04-19	tests: update stats for name changes	Nathan Binkert

2011-04-12	ARM: Fix stats for ARM_SE checkpoint restore fix.	Ali Saidi
	Register reads/writes done in startup() count against the stats while they don't count if done in initState().
2011-04-04	ARM: Update stats for previous changes.	Ali Saidi

2011-04-04	O3: Update stats for memory order violation checking patch.	Ali Saidi

2011-03-17	ARM: Update stats for the previous changes and add ARM_FS/O3 regression.	Ali Saidi

2011-03-17	Stats: Update the statistics for rfe patch.	Ali Saidi

2011-03-16	X86: Update the stats for gzip on x86 O3.	Gabe Black

2011-02-23	inorder: add 00.gzip and 60.bzip2 regression tests	Korey Sewell

2011-02-23	ARM: Update regression tests for preceeding changes.	Ali Saidi

2011-02-13	X86: Update stats for the improved branch detection/prediction.	Gabe Black

2011-02-13	X86: Update stats now that the dest reg isn't read unnecessarily to set flags.	Gabe Black

2011-02-13	X86: Update stats for the reduced register reads.	Gabe Black

2011-02-07	Stats: Re update stats.	Gabe Black

2011-02-05	X86: Add o3 regressions in SE mode.	Gabe Black
	Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-02	Stats: Update the x86 stats to reflect changing stupd to a store and update.	Gabe Black

2011-01-18	ARM/O3: Add regressions for ARM w/ O3 CPU.	Ali Saidi

2011-01-18	Stats: Update stats for previous set of patches.	Ali Saidi

2011-01-15	SPARC: Update stats for the call r15 as source change.	Gabe Black

2010-12-07	Stats: Fix stats for cumulative flags change.	Ali Saidi

2010-11-15	Stats: Update the O3 fetch stats for SPARC.	Gabe Black

2010-11-15	Regressions: Update regressions for SIMD opclass changes	Ali Saidi

2010-11-08	ARM: Update SE stats for TLB stats additions	Ali Saidi

2010-11-08	ARM: Add full-system regressions	Ali Saidi

2010-11-08	ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads.	Ali Saidi

2010-10-31	Ref output: Update refs for PCState change.	Gabe Black

2010-09-21	stats: update stats for previous cset	Steve Reinhardt
	Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
2010-09-09	stats: update stats for preceding coherence changes	Steve Reinhardt
	Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-08-25	ARM: Update regression tests for ldr/str microcode changes.	Ali Saidi

2010-08-17	tests: update reference config.ini files for previous cset	Steve Reinhardt
	Rename 'responder_set' to 'use_default_range'.
2010-07-27	ARM: Add regression tests	Ali Saidi

2010-06-06	tests: Update O3 ref outputs to reflect Lisa's dist format change.	m5test

2010-05-13	BPRED: Update regressions for tournament predictor fix.	Ali Saidi

2010-05-03	X86: Update stats for the updated auxilliary vectors.	Gabe Black

2010-02-25	stats: update stats for the changes I pushed re: shared cache occupancy	Lisa Hsu

2009-11-08	tests: update statistics for change caused by vsyscall support in x86	Nathan Binkert
	Caused by a slight change in memory layout.
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
	Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. --HG-- rename : src/python/m5/convert.py => src/python/m5/util/convert.py rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-08-08	X86: Update the stats for the slightly lengthened cmov.	Gabe Black

2009-07-06	tests: stats outputs now include CDFs, update tests that use those so ↵	Nathan Binkert
	they're easier to diff
2009-04-22	stats: update reference outputs now that compatibility is gone	Nathan Binkert
	Because of the initialization bug, it wasn't consistent anyway.
2009-04-22	Update stats for new single bad-address responder.	Steve Reinhardt
	Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-19	X86: Update the stats for the fix for CPUID.	Gabe Black

2009-04-15	Update stats after elimination of Unallocated state.	Steve Reinhardt
	Somehow ending threads with halt() instead of deallocate() reduces the squash count on o3 by 1 (and a few other similarly trivial changes).