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2012-01-25stats: Update stats for final tick and memory bandwidth patchesAli Saidi
2012-01-10X86 Regressions: Update stats due to fence instructionNilay Vaish
2011-12-01imported patch ext/stats_updates.patchAli Saidi
--HG-- extra : rebase_source : 4697ba9eb1ca8c67fe0915fb8340d7d4ae94caba
2011-11-30SPARC: update SE stats for FP fixAli Saidi
--HG-- extra : rebase_source : 954a009a9f8eef6cae6050ee99f264e0fb456f85
2011-11-17Regression: Update statistics for x86 long regression testsNilay Vaish
This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-09-13O3: Update stats for new ordering fix.Ali Saidi
2011-08-19StoreSet: Update stats for store-set clearingAli Saidi
2011-08-19O3: Update stats for LSQ changes.Ali Saidi
2011-07-10O3: Update stats for fetch and bp changes.Ali Saidi
2011-07-02Stats: Update stats for the x86 store fault fix.Gabe Black
2011-06-20alpha:o3:simple: update simout/err filesKorey Sewell
A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-19inorder: update SE regressionsKorey Sewell
2011-06-12sparc: update long regressionsKorey Sewell
2011-05-23Stats: Update stats for minor O3 changes below.Ali Saidi
2011-05-13ARM: Fix up stats for previous changes to condition codesAli Saidi
2011-04-22tests: updates for stat name changeNathan Binkert
2011-04-19tests: update stats for name changesNathan Binkert
2011-04-12ARM: Fix stats for ARM_SE checkpoint restore fix.Ali Saidi
Register reads/writes done in startup() count against the stats while they don't count if done in initState().
2011-04-04ARM: Update stats for previous changes.Ali Saidi
2011-04-04O3: Update stats for memory order violation checking patch.Ali Saidi
2011-03-17ARM: Update stats for the previous changes and add ARM_FS/O3 regression.Ali Saidi
2011-03-17Stats: Update the statistics for rfe patch.Ali Saidi
2011-03-16X86: Update the stats for gzip on x86 O3.Gabe Black
2011-02-23inorder: add 00.gzip and 60.bzip2 regression testsKorey Sewell
2011-02-23ARM: Update regression tests for preceeding changes.Ali Saidi
2011-02-13X86: Update stats for the improved branch detection/prediction.Gabe Black
2011-02-13X86: Update stats now that the dest reg isn't read unnecessarily to set flags.Gabe Black
2011-02-13X86: Update stats for the reduced register reads.Gabe Black
2011-02-07Stats: Re update stats.Gabe Black
2011-02-05X86: Add o3 regressions in SE mode.Gabe Black
Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-02Stats: Update the x86 stats to reflect changing stupd to a store and update.Gabe Black
2011-01-18ARM/O3: Add regressions for ARM w/ O3 CPU.Ali Saidi
2011-01-18Stats: Update stats for previous set of patches.Ali Saidi
2011-01-15SPARC: Update stats for the call r15 as source change.Gabe Black
2010-12-07Stats: Fix stats for cumulative flags change.Ali Saidi
2010-11-15Stats: Update the O3 fetch stats for SPARC.Gabe Black
2010-11-15Regressions: Update regressions for SIMD opclass changesAli Saidi
2010-11-08ARM: Update SE stats for TLB stats additionsAli Saidi
2010-11-08ARM: Add full-system regressionsAli Saidi
2010-11-08ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads.Ali Saidi
2010-10-31Ref output: Update refs for PCState change.Gabe Black
2010-09-21stats: update stats for previous csetSteve Reinhardt
Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
2010-09-09stats: update stats for preceding coherence changesSteve Reinhardt
Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-08-25ARM: Update regression tests for ldr/str microcode changes.Ali Saidi
2010-08-17tests: update reference config.ini files for previous csetSteve Reinhardt
Rename 'responder_set' to 'use_default_range'.
2010-07-27ARM: Add regression testsAli Saidi
2010-06-06tests: Update O3 ref outputs to reflect Lisa's dist format change.m5test
2010-05-13BPRED: Update regressions for tournament predictor fix.Ali Saidi
2010-05-03X86: Update stats for the updated auxilliary vectors.Gabe Black
2010-02-25stats: update stats for the changes I pushed re: shared cache occupancyLisa Hsu