summaryrefslogtreecommitdiff
path: root/tests/long/60.bzip2
AgeCommit message (Collapse)Author
2012-01-25stats: Update stats for final tick and memory bandwidth patchesAli Saidi
2012-01-10X86 Regressions: Update stats due to fence instructionNilay Vaish
2011-12-01imported patch ext/stats_updates.patchAli Saidi
--HG-- extra : rebase_source : 4697ba9eb1ca8c67fe0915fb8340d7d4ae94caba
2011-09-13O3: Update stats for new ordering fix.Ali Saidi
2011-08-19StoreSet: Update stats for store-set clearingAli Saidi
2011-08-19O3: Update stats for LSQ changes.Ali Saidi
2011-07-10O3: Update stats for fetch and bp changes.Ali Saidi
2011-06-20alpha:o3:simple: update simout/err filesKorey Sewell
A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-19inorder: update SE regressionsKorey Sewell
2011-05-23Stats: Update stats for minor O3 changes below.Ali Saidi
2011-05-13ARM: Fix up stats for previous changes to condition codesAli Saidi
2011-04-22tests: updates for stat name changeNathan Binkert
2011-04-19tests: update stats for name changesNathan Binkert
2011-04-12ARM: Fix stats for ARM_SE checkpoint restore fix.Ali Saidi
Register reads/writes done in startup() count against the stats while they don't count if done in initState().
2011-04-04ARM: Update stats for previous changes.Ali Saidi
2011-04-04O3: Update stats for memory order violation checking patch.Ali Saidi
2011-03-17ARM: Update stats for the previous changes and add ARM_FS/O3 regression.Ali Saidi
2011-02-27inorder: bzip2 regression updateKorey Sewell
2011-02-23inorder: add 00.gzip and 60.bzip2 regression testsKorey Sewell
2011-02-23ARM: Update regression tests for preceeding changes.Ali Saidi
2011-02-13X86: Update stats now that the dest reg isn't read unnecessarily to set flags.Gabe Black
2011-02-13X86: Update stats for the reduced register reads.Gabe Black
2011-02-07Stats: Re update stats.Gabe Black
2011-02-02Stats: Update the x86 stats to reflect changing stupd to a store and update.Gabe Black
2011-01-18ARM/O3: Add regressions for ARM w/ O3 CPU.Ali Saidi
2011-01-18Stats: Update stats for previous set of patches.Ali Saidi
2010-11-15Regressions: Update regressions for SIMD opclass changesAli Saidi
2010-11-08ARM: Update SE stats for TLB stats additionsAli Saidi
2010-11-08ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads.Ali Saidi
2010-09-21stats: update stats for previous csetSteve Reinhardt
Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
2010-09-09stats: update stats for preceding coherence changesSteve Reinhardt
Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-08-25ARM: Update regression tests for ldr/str microcode changes.Ali Saidi
2010-08-17tests: update reference config.ini files for previous csetSteve Reinhardt
Rename 'responder_set' to 'use_default_range'.
2010-07-27ARM: Add regression testsAli Saidi
2010-06-06tests: Update O3 ref outputs to reflect Lisa's dist format change.m5test
2010-05-19BPRED: Update one missing regressionAli Saidi
2010-05-03X86: Update stats for the updated auxilliary vectors.Gabe Black
2010-02-25stats: update stats for the changes I pushed re: shared cache occupancyLisa Hsu
2009-11-08tests: update statistics for change caused by vsyscall support in x86Nathan Binkert
Caused by a slight change in memory layout.
2009-10-24tests: update test for slight change due to the change in brk.Nathan Binkert
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. --HG-- rename : src/python/m5/convert.py => src/python/m5/util/convert.py rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-08-08X86: Update the stats for the slightly lengthened cmov.Gabe Black
2009-07-06tests: stats outputs now include CDFs, update tests that use those so ↵Nathan Binkert
they're easier to diff
2009-04-22stats: update reference outputs now that compatibility is goneNathan Binkert
Because of the initialization bug, it wasn't consistent anyway.
2009-04-22Update stats for new single bad-address responder.Steve Reinhardt
Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-19X86: Update the stats for the fix for CPUID.Gabe Black
2009-04-15Update stats after elimination of Unallocated state.Steve Reinhardt
Somehow ending threads with halt() instead of deallocate() reduces the squash count on o3 by 1 (and a few other similarly trivial changes).
2009-04-08tests: update tests for TLB unificationNathan Binkert
2009-03-07tests: update tests because of changes in stat names and in the stats packageNathan Binkert
2009-02-25CPU: Update stats now that there's no fetch in the middle of macroops.Gabe Black