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2011-05-04O3/ARM: Update stats for recent changes.Ali Saidi
2011-04-22tests: updates for stat name changeNathan Binkert
2011-04-19tests: update stats for name changesNathan Binkert
2011-04-12ARM: Fix stats for ARM_SE checkpoint restore fix.Ali Saidi
Register reads/writes done in startup() count against the stats while they don't count if done in initState().
2011-04-04ARM: Update stats for previous changes.Ali Saidi
2011-04-04O3: Update stats for memory order violation checking patch.Ali Saidi
2011-03-17ARM: Update stats for the previous changes and add ARM_FS/O3 regression.Ali Saidi
2011-02-23ARM: Update regression tests for preceeding changes.Ali Saidi
2011-02-18m5: merge inorder/release-notes/make_release changesKorey Sewell
2011-02-18inorder: regr-update: reduce dynamic mem. use to speedup simsKorey Sewell
previous changesets took a closer look at memory mgmt in the inorder model and sought to avoid dynamic memory mgmt (for access to pipeline resources) as much as possible. For the regressions that were run, the sims are about 2x speedup from changeset 7726 which is the last change since the recent commits in Feb. (note: these regressions now are 4-issue CPUs instead of just 1-issue)
2011-02-13X86: Update stats for the improved branch detection/prediction.Gabe Black
2011-02-13X86: Update stats now that the dest reg isn't read unnecessarily to set flags.Gabe Black
2011-02-13X86: Update stats for the reduced register reads.Gabe Black
2011-02-12inorder:regress: host-inst-rate improved ~58%Korey Sewell
there are still only a few inorder benchmark but for the lengthier benchmarks (twolf and vortext) the latest changes to how instruction scheduling (how instructions figure out what they want to do on each pipeline stage in the inorder model) were able to improve performance by a nice amount... The latest results for the inorder model process about 100k insts/second (note: 58% is over the last time run on 64-bit pool machines at UM)
2011-02-07Stats: Re update stats.Gabe Black
2011-02-05X86: Add o3 regressions in SE mode.Gabe Black
Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-04imported patch regression_updatesKorey Sewell
2011-02-02Stats: Update the x86 stats to reflect changing stupd to a store and update.Gabe Black
2011-01-18ARM/O3: Add regressions for ARM w/ O3 CPU.Ali Saidi
2011-01-18Stats: Update stats for previous set of patches.Ali Saidi
2010-11-15Regressions: Update regressions for SIMD opclass changesAli Saidi
2010-11-08ARM: Update SE stats for TLB stats additionsAli Saidi
2010-11-08ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads.Ali Saidi
2010-09-21stats: update stats for previous csetSteve Reinhardt
Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
2010-09-09stats: update stats for preceding coherence changesSteve Reinhardt
Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-08-25ARM: Update regression tests for ldr/str microcode changes.Ali Saidi
2010-08-17tests: update reference config.ini files for previous csetSteve Reinhardt
Rename 'responder_set' to 'use_default_range'.
2010-07-27ARM: Add regression testsAli Saidi
2010-06-25inorder: update regressions from RAS fixKorey Sewell
2010-06-24inorder: update regressionsKorey Sewell
2010-06-23inorder: update regressionsKorey Sewell
2010-06-06tests: Update O3 ref outputs to reflect Lisa's dist format change.m5test
2010-05-13BPRED: Update regressions for tournament predictor fix.Ali Saidi
2010-05-03X86: Update stats for the updated auxilliary vectors.Gabe Black
2010-04-11inorder: update regressions for fwd-ing patchKorey Sewell
2010-03-27inorder: update twolf/vortex regressionsKorey Sewell
2010-03-23inorder: update twolf regressionKorey Sewell
2010-02-25stats: update stats for the changes I pushed re: shared cache occupancyLisa Hsu
2010-01-31inorder: twolf alpha regressionKorey Sewell
2009-11-08tests: update statistics for change caused by vsyscall support in x86Nathan Binkert
Caused by a slight change in memory layout.
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. --HG-- rename : src/python/m5/convert.py => src/python/m5/util/convert.py rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-08-17X86: Update stats for new SSE instructions.Gabe Black
2009-08-08X86: Update the stats for the slightly lengthened cmov.Gabe Black
2009-07-06tests: stats outputs now include CDFs, update tests that use those so ↵Nathan Binkert
they're easier to diff
2009-07-04inorder: Fix up some reference stats.Gabe Black
2009-05-12inorder-regress: add twolf ALPHA-SEKorey Sewell
2009-04-22stats: update reference outputs now that compatibility is goneNathan Binkert
Because of the initialization bug, it wasn't consistent anyway.
2009-04-22Update stats for new single bad-address responder.Steve Reinhardt
Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-19X86: Update the stats for the fix for CPUID.Gabe Black
2009-04-15Update stats after elimination of Unallocated state.Steve Reinhardt
Somehow ending threads with halt() instead of deallocate() reduces the squash count on o3 by 1 (and a few other similarly trivial changes).