Age | Commit message (Collapse) | Author |
|
The switcheroo tests only really serve to check functional
correctness. Checking for stat differences in them just increases the
size of reference diffs.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
|
|
|
|
Change-Id: Ic827213134b199446822f128b81d4a480e777fee
|
|
--HG--
extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
|
|
Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.
|
|
Small changes to the branch predictor and BTB caused stats changes
throughout.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
|
|
|
|
Very small differences in IQ-specific O3 stats.
|
|
|
|
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
|
|
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
|
|
|
|
|
|
|
|
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
|
|
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
|
|
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
|
|
|
|
|
|
This patch updates the stats to reflect the changes to the DRAM
controller.
|
|
|
|
|
|
|
|
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
|
|
Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
|
|
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.
The main reason for bundling them up is to minimise the changeset
size.
|
|
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
|
|
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
|
|
|
|
|
|
This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
|
|
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
|
|
|
|
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
|
|
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
|
|
|
|
This changeset adds a set of tests that stress the CPU switching
code. It adds the following test configurations:
* tsunami-switcheroo-full -- Alpha system (atomic, timing, O3)
* realview-switcheroo-atomic -- ARM system (atomic<->atomic)
* realview-switcheroo-timing -- ARM system (timing<->timing)
* realview-switcheroo-o3 -- ARM system (O3<->O3)
* realview-switcheroo-full -- ARM system (atomic, timing, O3)
Reference data is provided for the 10.linux-boot test case. All of the
tests trigger a CPU switch once per millisecond during the boot
process.
The in-order CPU model was not included in any of the tests as it does
not support CPU handover.
|