gem5 - gem5

Age	Commit message (Collapse)	Author
2013-03-27	regressions: update due to cache latency fix	Nilay Vaish

2013-03-26	stats: Update stats to reflect bus retry changes	Andreas Hansson
	This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-04	stats: update patches for branch predictor and fetch updates.	Ali Saidi

2013-03-01	stats: Update stats to reflect SimpleDRAM changes	Andreas Hansson
	This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-02-15	stats: update regressions for o3 changes in renaming and translation.	Ali Saidi

2013-01-31	stats: Update stats for regressions using SimpleDDR3	Andreas Hansson
	This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-24	regressions: update stats due to branch predictor changes	Nilay Vaish
	The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-08	stats: update stats for previous six changes	Ali Saidi

2013-01-07	stats: update stats for previous changes.	Ali Saidi

2013-01-07	tests: Add CPU switching tests	Andreas Sandberg
	This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.