gem5 - gem5

Age	Commit message (Collapse)	Author
2014-09-03	stats: Update stats for CPU and cache changes	Andreas Hansson
	This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-01	stats: updates due to recent ruby and x86 changes	Nilay Vaish
	Also updates many out of date config files.
2014-05-09	stats: Bump stats for the fixes, and mostly DRAM controller changes	Andreas Hansson

2014-03-23	stats: Update stats for DRAM changes	Andreas Hansson
	This patch updates the stats to reflect the changes to the DRAM controller.
2014-02-19	arm: Bump stats after FS config script update	Andreas Hansson
	This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-16	stats: updates due to branch predictor warming	Nilay Vaish

2014-01-24	stats: update stats for ARMv8 changes	Ali Saidi

2014-01-24	stats: update stats for cache occupancy and clock domain changes	Ali Saidi

2013-11-26	stats: updates due to changes to ticksToCycles()	Nilay Vaish

2013-11-01	stats: Bump stats to match DRAM controller changes	Andreas Hansson
	This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-09-28	tests: update reference outputs	Steve Reinhardt
	Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-08-19	stats: Cumulative stats update	Andreas Hansson
	This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-06-27	stats: Update stats for monitor, cache and bus changes	Andreas Hansson
	This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-05-30	stats: Update the stats to reflect bus and memory changes	Andreas Hansson
	This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-04-22	stats: Update stats for O3 switching fix.	Ali Saidi

2013-03-27	regressions: update due to cache latency fix	Nilay Vaish

2013-03-01	stats: Update stats to reflect SimpleDRAM changes	Andreas Hansson
	This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-01-31	stats: Update stats for regressions using SimpleDDR3	Andreas Hansson
	This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-24	regressions: update stats due to branch predictor changes	Nilay Vaish
	The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-07	tests: Add CPU switching tests	Andreas Sandberg
	This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.