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The statistics for 30.eio-mp, pc-simple-timing-ruby tests are being updated
to incorporate the changes due to recent patches.
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This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
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This patch extends the existing system builders to also include a
syscall-emulation builder. This builder is deployed in all
syscall-emulation regressions that do not involve Ruby,
i.e. o3-timing, simple-timing and simple-atomic, as well as the
multi-processor regressions o3-timing-mp, simple-timing-mp and
simple-atomic-mp (the latter are only used by SPARC at this point).
The values chosen for the cache sizes match those that were used in
the existing config scripts (despite being on the large
side). Similarly, a mem_class parameter is added to the builder base
class to enable simple-atomic to use SimpleMemory and o3-timing to use
the default DDR3 configuration.
Due to the different order the ports are connected, the bus stats get
shuffled around for the multi-processor regressions. A separate patch
bumps the port indices. Besides this, all behaviour is exactly the
same.
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This patch prunes the 00.gzip regressions with the main motivation
being that it adds little (or no) coverage and requires a substantial
amount of run time.
A complete regression run, including compilation from a clean repo, is
almost 20% faster(!).
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This patch bumps the x86 stats to reflect the recent fixes.
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Ruby's controller statistics have been mostly moved to stats.txt now.
Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are
also being updated.
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This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
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This is due to op class, function call, walker patches.
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This patch merely bumps the stats to match the changes introduced in
changeset 35198406dd72.
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This patch bumps the stats for the failing vortex o3 regression.
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This patch updates the stats for the affected stats. All the changes
are minimal (in the <0.01% range).
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This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
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This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
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This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
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This patch bumps the stats for 20.parser for ARM o3-timing to reflect
a namechange of the branch predictor.
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The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
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This patch bumps the stats of mcf and twolf for the o3 CPU such that
the regressions pass.
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This changeset adds a set of tests that stress the CPU switching
code. It adds the following test configurations:
* tsunami-switcheroo-full -- Alpha system (atomic, timing, O3)
* realview-switcheroo-atomic -- ARM system (atomic<->atomic)
* realview-switcheroo-timing -- ARM system (timing<->timing)
* realview-switcheroo-o3 -- ARM system (O3<->O3)
* realview-switcheroo-full -- ARM system (atomic, timing, O3)
Reference data is provided for the 10.linux-boot test case. All of the
tests trigger a CPU switch once per millisecond during the boot
process.
The in-order CPU model was not included in any of the tests as it does
not support CPU handover.
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This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
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This patch updates the stats to reflect the change in the default
system clock from 1 THz to 1GHz. The changes are due to the DMA
devices now injecting requests at a lower pace.
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This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
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This patch updates the stats after removing the zero-time send used in
the DMA port.
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This patch brings the t1000 stats up to date.
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This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
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This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
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This patch updates the name of the l2 stats.
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