gem5 - gem5

Age	Commit message (Expand)	Author
2014-01-24	stats: update stats for cache occupancy and clock domain changes	Ali Saidi
2013-11-26	stats: updates due to changes to ticksToCycles()	Nilay Vaish
2013-11-01	stats: Bump stats to match DRAM controller changes	Andreas Hansson
2013-09-28	tests: update reference outputs	Steve Reinhardt
2013-08-19	stats: Cumulative stats update	Andreas Hansson
2013-06-27	stats: Update stats for monitor, cache and bus changes	Andreas Hansson
2013-05-30	stats: Update the stats to reflect bus and memory changes	Andreas Hansson
2013-03-27	regressions: update due to cache latency fix	Nilay Vaish
2013-03-26	stats: Update stats for cache retry event check	Andreas Hansson
2013-03-26	stats: Update stats to reflect bus retry changes	Andreas Hansson
2013-03-01	stats: Update stats to reflect SimpleDRAM changes	Andreas Hansson
2013-01-31	stats: Update stats for regressions using SimpleDDR3	Andreas Hansson
2013-01-24	regressions: update stats due to branch predictor changes	Nilay Vaish
2012-10-25	stats: Update the stats to reflect the 1GHz default system clock	Andreas Hansson
2012-10-25	stats: Update stats to reflect use of SimpleDRAM	Andreas Hansson
2012-10-15	Stats: Update stats for cache timings in cycles	Andreas Hansson
2012-09-18	Stats: Update stats to reflect SimpleMemory bandwidth	Andreas Hansson
2012-09-10	Device: Update stats for PIO and PCI latency change	Andreas Hansson
2012-07-27	stats: update stats for icache change not allowing dirty data	Ali Saidi
2012-07-09	Stats: Updates due to bus changes	Andreas Hansson
2012-06-29	Stats: Update stats for RAS and LRU fixes.	Ali Saidi
2012-06-05	all: Update stats for memory per master and total fix.	Ali Saidi
2012-05-09	stats: update stats for no_value -> nan	Nathan Binkert
2012-02-12	stats: update stats for insts/ops and master id changes	Ali Saidi
2012-01-28	SE/FS: Make both SE and FS tests available all the time.	Gabe Black