Age | Commit message (Collapse) | Author | |
---|---|---|---|
2015-03-02 | stats: Update stats to reflect cache and interconnect changes | Andreas Hansson | |
This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU. | |||
2015-01-04 | stats: changes due to recent changesets. | Nilay Vaish | |
2014-12-23 | stats: Bump stats for decoder, TLB, prefetcher and DRAM changes | Andreas Hansson | |
Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. | |||
2014-12-02 | stats: Bump stats for fixes, mostly TLB and WriteInvalidate | Andreas Hansson | |
2014-10-30 | arm, tests: Forgot the system.terminal files for the new regressions. | Ali Saidi | |
2014-10-29 | arm, tests: Add 64-bit ARM regression tests | Ali Saidi | |