| Age | Commit message (Expand) | Author |
|---|
| 2015-11-16 | stats: updates due to recent chagnesets | Nilay Vaish |
| 2015-11-06 | stats: Update stats to match cache changes | Andreas Hansson |
| 2015-10-10 | stats: Update for UDelayEvent quiesce change | Joel Hestness |
| 2015-09-25 | stats: Update stats to reflect snoop-filter changes | Andreas Hansson |
| 2015-09-15 | stats: updates due to recent changesets including d0934b57735a | Nilay Vaish |
| 2015-07-05 | stats: x86: update stats missed out on in preivous changeset | Nilay Vaish |
| 2015-07-03 | stats: Update stats for cache, crossbar and DRAM changes | Andreas Hansson |
| 2015-05-05 | stats: Update stats to reflect cache changes | Andreas Hansson |
| 2015-03-09 | stats: changes to due to recent set of patches | Nilay Vaish |
| 2015-03-02 | stats: Update stats to reflect cache and interconnect changes | Andreas Hansson |
| 2015-01-10 | stats: changes due to recent changesets. | Nilay Vaish |
| 2015-01-07 | stats: x86: Update stats for the CPUID change. | Gabe Black |
| 2015-01-04 | stats: changes due to recent changesets. | Nilay Vaish |
| 2014-12-23 | stats: Bump stats for decoder, TLB, prefetcher and DRAM changes | Andreas Hansson |
| 2014-12-02 | stats: Bump stats for fixes, mostly TLB and WriteInvalidate | Andreas Hansson |
| 2014-11-21 | x86: Update stats for the new Linux delay port. | Gabe Black |
| 2014-11-17 | x86: Update the stats for the x86 FS o3 boot test. | Gabe Black |
| 2014-10-29 | tests: Update regressions for the new kernels and various preceeding fixes. | Ali Saidi |
| 2014-10-11 | stats: updates due to changes to x86, stale configs. | Nilay Vaish |
| 2014-10-09 | stats: Add DRAM power statistics to reference output | Andreas Hansson |
| 2014-09-20 | stats: Bump stats for filter, crossbar and config changes | Andreas Hansson |
| 2014-09-03 | stats: Update stats for CPU and cache changes | Andreas Hansson |
| 2014-09-01 | stats: updates due to recent ruby and x86 changes | Nilay Vaish |
| 2014-05-09 | stats: Bump stats for the fixes, and mostly DRAM controller changes | Andreas Hansson |
| 2014-03-23 | stats: Update stats for DRAM changes | Andreas Hansson |
| 2014-02-16 | stats: updates due to branch predictor warming | Nilay Vaish |
| 2014-01-24 | stats: update stats for cache occupancy and clock domain changes | Ali Saidi |
| 2013-11-26 | stats: updates due to changes to ticksToCycles() | Nilay Vaish |
| 2013-11-01 | stats: Bump stats to match DRAM controller changes | Andreas Hansson |
| 2013-11-01 | stats: Bump stats after shifting to SimpleMemory | Andreas Hansson |
| 2013-10-16 | test: update stats | Steve Reinhardt |
| 2013-10-02 | stats: Update x86 stats after x87 fixes | Andreas Sandberg |
| 2013-09-28 | tests: update reference outputs | Steve Reinhardt |
| 2013-08-19 | stats: Cumulative stats update | Andreas Hansson |
| 2013-06-27 | stats: Update stats for monitor, cache and bus changes | Andreas Hansson |
| 2013-05-30 | stats: Update the stats to reflect bus and memory changes | Andreas Hansson |
| 2013-05-21 | x86, regressions: updates stats | Nilay Vaish |
| 2013-04-23 | x86, stats: updates due to lret bugfix | Nilay Vaish |
| 2013-03-29 | regressions: updates due to changes to o3 cpu, x86 memory map | Nilay Vaish |
| 2013-03-26 | stats: Update stats for cache retry event check | Andreas Hansson |
| 2013-03-26 | stats: Update stats to reflect bus retry changes | Andreas Hansson |
| 2013-03-01 | stats: Update stats to reflect SimpleDRAM changes | Andreas Hansson |
| 2013-01-31 | stats: Update stats for regressions using SimpleDDR3 | Andreas Hansson |
| 2013-01-24 | regressions: update stats due to branch predictor changes | Nilay Vaish |
| 2013-01-15 | x86 regressions: updates due to new instructions and cpuid | Nilay Vaish |
| 2012-12-06 | regression test: update a couple of config.ini files | Nilay Vaish |
| 2012-10-25 | stats: Update the stats to reflect the 1GHz default system clock | Andreas Hansson |
| 2012-10-25 | stats: Update stats to reflect use of SimpleDRAM | Andreas Hansson |
| 2012-10-15 | Stats: Update stats for cache timings in cycles | Andreas Hansson |
| 2012-10-15 | Stats: Update stats for new default L1-to-L2 bus clock and width | Andreas Hansson |
